JAJSST5A June   2015  – February 2024 LV14540

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Fixed Frequency Peak Current Mode Control
      2. 6.3.2  Slope Compensation
      3. 6.3.3  Pulse Skipping Mode
      4. 6.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 6.3.5  Adjustable Output Voltage
      6. 6.3.6  Enable and Adjustable Undervoltage Lockout
      7. 6.3.7  External Soft Start
      8. 6.3.8  Switching Frequency and Synchronization (RT/SYNC)
      9. 6.3.9  Overcurrent and Short-Circuit Protection
      10. 6.3.10 Overvoltage Protection
      11. 6.3.11 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Active Mode
      3. 6.4.3 CCM Mode
      4. 6.4.4 Light Load Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Voltage Set-Point
        2. 7.2.2.2 Switching Frequency
        3. 7.2.2.3 Output Inductor Selection
        4. 7.2.2.4 Output Capacitor Selection
        5. 7.2.2.5 Schottky Diode Selection
        6. 7.2.2.6 Input Capacitor Selection
        7. 7.2.2.7 Bootstrap Capacitor Selection
        8. 7.2.2.8 Soft-start Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.3 Pulse Skipping Mode

The LV14540 operates in pulse skipping mode (PSM) at light load current to improve efficiency by reducing switching and gate drive losses. If the output voltage is within regulation and the peak switching current at the end of any switching cycle is below the current threshold of 300 mA, the device enters PSM. The PSM current threshold is the peak switch current level corresponding to a nominal internal COMP voltage of 400 mV.

When in PSM, the internal COMP voltage is clamped at 400 mV, the high-side MOSFET is inhibited, and the device draws about 120 μA input quiescent current. Because the device is not switching, the output voltage begins to decay. The voltage control loop responds to the falling output voltage by increasing the internal COMP voltage. The high-side MOSFET is enabled and switching resumes when the error amplifier lifts internal COMP voltage above 400 mV. The output voltage recovers to the regulated value, and internal COMP voltage eventually falls below the PSM threshold at which time the device again enters PSM.