JAJSP96E April   2005  – October 2022 MAX3243E

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  ESD Ratings - IEC Specifications
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Driver Electrical Characteristics
    8. 7.8  Receiver, Electrical Characteristics
    9. 7.9  Auto-Powerdown Electrical Characteristics
    10. 7.10 Driver Switching Characteristics
    11. 7.11 Receiver Switching Characteristics
    12. 7.12 Auto-Powerdown Switching Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ESD Protection
          1. 10.2.2.1.1 ESD Test Conditions
          2. 10.2.2.1.2 Human Body Model (HBM)
          3. 10.2.2.1.3 IEC61000-4-2 (Formerly Known as IEC1000-4-2)
          4. 10.2.2.1.4 Machine Model
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Example
        1.       Device and Documentation Support
          1. 11.1 Receiving Notification of Documentation Updates
          2. 11.2 サポート・リソース
          3. 11.3 Trademarks
          4. 11.4 Electrostatic Discharge Caution
          5. 11.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.11 Receiver Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETERTEST CONDITIONSTYP(2)UNIT
tPLHPropagation delay time, low- to high-level outputCL = 150 pF, See Figure 8-3150ns
tPHLPropagation delay time, high- to low-level output150ns
tenOutput enable timeCL = 150 pF, RL = 3 kΩ,
See Figure 8-4		200ns
tdisOutput disable time200ns
tsk(p)Puse skew(3)See Figure 8-350ns
(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(3) Pulse skew is defined as |tPLH - tPHL| of each channel of the same device.