SLLSFX9 December   2024 MCF8316D

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Output Stage
      2. 6.3.2  Device Interface
        1. 6.3.2.1 Interface - Control and Monitoring
        2. 6.3.2.2 I2C Interface
      3. 6.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 6.3.3.1 Buck in Inductor Mode
        2. 6.3.3.2 Buck in Resistor mode
        3. 6.3.3.3 Buck Regulator with External LDO
        4. 6.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 6.3.3.5 Mixed Mode Buck Operation and Control
      4. 6.3.4  AVDD Linear Voltage Regulator
      5. 6.3.5  Charge Pump
      6. 6.3.6  Slew Rate Control
      7. 6.3.7  Cross Conduction (Dead Time)
      8. 6.3.8  Motor Control Input Sources
        1. 6.3.8.1 Analog-Mode Motor Control
        2. 6.3.8.2 PWM-Mode Motor Control
        3. 6.3.8.3 I2C-based Motor Control
        4. 6.3.8.4 Frequency-Mode Motor Control
        5. 6.3.8.5 Input Reference Profiles
          1. 6.3.8.5.1 Linear Control Profiles
          2. 6.3.8.5.2 Staircase Control Profiles
          3. 6.3.8.5.3 Forward-Reverse Profiles
          4. 6.3.8.5.4 Multi-Reference Mode Operation
          5. 6.3.8.5.5 Input Reference Transfer Function without Profiler
      9. 6.3.9  Starting the Motor Under Different Initial Conditions
        1. 6.3.9.1 Case 1 – Motor is Stationary
        2. 6.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 6.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 6.3.10 Motor Start Sequence (MSS)
        1. 6.3.10.1 Initial Speed Detect (ISD)
        2. 6.3.10.2 Motor Resynchronization
        3. 6.3.10.3 Reverse Drive
          1. 6.3.10.3.1 Reverse Drive Tuning
        4. 6.3.10.4 Motor Start-up
          1. 6.3.10.4.1 Align
          2. 6.3.10.4.2 Double Align
          3. 6.3.10.4.3 Initial Position Detection (IPD)
            1. 6.3.10.4.3.1 IPD Operation
            2. 6.3.10.4.3.2 IPD Release Mode
            3. 6.3.10.4.3.3 IPD Advance Angle
          4. 6.3.10.4.4 Slow First Cycle Startup
          5. 6.3.10.4.5 Open Loop
          6. 6.3.10.4.6 Transition from Open to Closed Loop
      11. 6.3.11 Closed Loop Operation
        1. 6.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 6.3.11.2 Speed PI Control
        3. 6.3.11.3 Current PI Control
        4. 6.3.11.4 Power Control Mode
        5. 6.3.11.5 Current (Torque) Control Mode
        6. 6.3.11.6 Modulation Index Control
        7. 6.3.11.7 Overmodulation
        8. 6.3.11.8 Motor Speed Limit
        9. 6.3.11.9 Input DC Power Limit
      12. 6.3.12 Flux Weakening Control
      13. 6.3.13 Motor Parameters
        1. 6.3.13.1 Motor Resistance
        2. 6.3.13.2 Motor Inductance
        3. 6.3.13.3 Motor Back-EMF constant
      14. 6.3.14 Motor Parameter Extraction Tool (MPET)
      15. 6.3.15 Anti-Voltage Surge (AVS)
      16. 6.3.16 Active Braking
      17. 6.3.17 Output PWM Switching Frequency
      18. 6.3.18 PWM Dithering
      19. 6.3.19 PWM Modulation Schemes
      20. 6.3.20 Dead Time Compensation
      21. 6.3.21 Motor Stop Options
        1. 6.3.21.1 Coast (Hi-Z) Mode
        2. 6.3.21.2 Recirculation Mode
        3. 6.3.21.3 Low-Side Braking
        4. 6.3.21.4 High-Side Braking
        5. 6.3.21.5 Active Spin-Down
      22. 6.3.22 Align Braking
      23. 6.3.23 FG Configuration
        1. 6.3.23.1 FG Output Frequency
        2. 6.3.23.2 FG during Open and Closed Loop States
        3. 6.3.23.3 FG during Fault and Idle States
      24. 6.3.24 Protections
        1. 6.3.24.1  VM Supply Undervoltage Lockout
        2. 6.3.24.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 6.3.24.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 6.3.24.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 6.3.24.5  Overvoltage Protection (OVP)
        6. 6.3.24.6  Overcurrent Protection (OCP)
          1. 6.3.24.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 6.3.24.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 6.3.24.7  Buck Overcurrent Protection
        8. 6.3.24.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 6.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown
          2. 6.3.24.8.2 HW_LOCK_ILIMIT Automatic Recovery
          3. 6.3.24.8.3 HW_LOCK_ILIMIT Report Only
          4. 6.3.24.8.4 HW_LOCK_ILIMIT Disabled
        9. 6.3.24.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 6.3.24.9.1 LOCK_ILIMIT Latched Shutdown
          2. 6.3.24.9.2 LOCK_ILIMIT Automatic Recovery
          3. 6.3.24.9.3 LOCK_ILIMIT Report Only
          4. 6.3.24.9.4 LOCK_ILIMIT Disabled
        10. 6.3.24.10 Motor Lock Detection
          1. 6.3.24.10.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 6.3.24.10.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 6.3.24.10.3 Lock3: No-Motor Fault (NO_MTR)
        11. 6.3.24.11 Motor Lock (MTR_LCK)
          1. 6.3.24.11.1 MTR_LCK Latched Shutdown
          2. 6.3.24.11.2 MTR_LCK Automatic Recovery
          3. 6.3.24.11.3 MTR_LCK Report Only
          4. 6.3.24.11.4 MTR_LCK Disabled
        12. 6.3.24.12 EEPROM Fault
        13. 6.3.24.13 I2C CRC Fault
        14. 6.3.24.14 Minimum VM (Undervoltage) Protection
        15. 6.3.24.15 Maximum VM (Overvoltage) Protection
        16. 6.3.24.16 MPET Faults
        17. 6.3.24.17 IPD Faults
        18. 6.3.24.18 FET Thermal Warning (OTW)
        19. 6.3.24.19 FET Thermal Shutdown (TSD_FET)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Standby Mode
        3. 6.4.1.3 Fault Reset (CLR_FLT)
    5. 6.5 External Interface
      1. 6.5.1 DRVOFF Functionality
      2. 6.5.2 DAC outputs
      3. 6.5.3 Current Sense Output
      4. 6.5.4 Oscillator Source
        1. 6.5.4.1 External Clock Source
      5. 6.5.5 External Watchdog
    6. 6.6 EEPROM access and I2C interface
      1. 6.6.1 EEPROM Access
        1. 6.6.1.1 EEPROM Write
        2. 6.6.1.2 EEPROM Read
        3. 6.6.1.3 EEPROM Security
      2. 6.6.2 I2C Serial Interface
        1. 6.6.2.1 I2C Data Word
        2. 6.6.2.2 I2C Write Transaction
        3. 6.6.2.3 I2C Read Transaction
        4. 6.6.2.4 I2C Communication Protocol Packet Examples
        5. 6.6.2.5 I2C Clock Stretching
        6. 6.6.2.6 CRC Byte Calculation
    7. 6.7 EEPROM (Non-Volatile) Register Map
      1. 6.7.1 Algorithm_Configuration Registers
      2. 6.7.2 Fault_Configuration Registers
      3. 6.7.3 Hardware_Configuration Registers
      4. 6.7.4 Internal_Algorithm_Configuration Registers
    8. 6.8 RAM (Volatile) Register Map
      1. 6.8.1 Fault_Status Registers
      2. 6.8.2 System_Status Registers
      3. 6.8.3 Device_Control Registers
      4. 6.8.4 Algorithm_Control Registers
      5. 6.8.5 Algorithm_Variables Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Application Curves
        1. 7.2.1.1 Motor startup
        2. 7.2.1.2 MPET
        3. 7.2.1.3 Dead time compensation
        4. 7.2.1.4 Auto handoff
        5. 7.2.1.5 Anti voltage surge (AVS)
        6. 7.2.1.6 Real time variable tracking using DACOUT
  9. 8 Power Supply Recommendations
    1. 8.1 Bulk Capacitance
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
      1. 9.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Support Resources
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

6.3.24 Protections

The MCF8316D is protected from a host of fault events including motor lock, VM undervoltage, AVDD undervoltage, buck undervoltage, charge pump undervoltage, overtemperature and overcurrent events. Table 6-6 summarizes the response, recovery modes, power stage status, reporting mechanism for different faults.

Note:
  1. Actionable faults (latched or retry) are always reported on nFAULT pin (as logic low).
  2. Actionable faults (latched or retry) are reported on ALARM pin (as logic high) when ALARM_PIN_EN is set to 1b.
  3. Report only faults are reported on nFAULT (as logic low) only when ALARM_PIN_EN is set to 0b. When ALARM_PIN_EN is set to 1b, report only faults are reported only on ALARM pin (as logic high) while nFAULT stays high (external or internal pull-up).
  4. Priority order for multi-fault scenarios is latched > slower retry time fault > faster retry time fault > report only fault. For example, if a latched and retry fault happen simultaneously, the device stays latched in fault mode until user issues clear fault command by writing 1b to CLR_FLT. If two retry faults with different retry times happen simultaneously, the device retries only after the longer (slower) retry time lapses.
  5. Recovery refers only to state of FETs (Hi-Z or active) after the fault condition is removed. Automatic indicates that the device automatically recovers (and FETs are active) when retry time lapses after the fault condition is removed. Latched indicates that the device waits for clearing of fault condition (by writing 1b to CLR_FLT bit) to make the FETs active again.
  6. Actionable (latched or retry) faults can take up to 200-ms after fault response (FETs in Hi-Z) to be reported on nFAULT pin (as logic low), ALARM pin (as logic high) and fault status registers.
  7. Latched faults can take up to 200-ms after CLR_FLT command is issued (over I2C) to be cleared.
  8. The fault state is latched when the cumulative number of automatic retry attempts (AUTO_RETRY_TIMES ≠ 000b) for all faults configured in automatic retry mode is reached. In this case, it is necessary to write 1b to CLR_FLT_RETRY_COUNT bit when writing 1b to CLR_FLT bit in ALGO_CTRL1 register to reset the retry counter to zero while clearing the latched fault state.
Table 6-6 Fault Action and Response
FAULT CONDITION CONFIGURATION REPORT FETs DIGITAL RECOVERY
VM undervoltage VVM < VUVLO (falling) — — Hi-Z Disabled Automatic:
VVM > VUVLO (rising)
AVDD undervoltage VAVDD < VAVDD_UV (falling) — — Hi-Z Disabled Automatic:
VAVDD > VAVDD_UV (rising)
Buck undervoltage
(BUCK_UV)		 VFB_BK < VBK_UV (falling) — — Active/Hi-Z Active/Disabled Automatic:
VFB_BK > VBK_UV (rising)
Charge pump undervoltage
(VCP_UV)		 VCP < VCPUV (falling) — nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Automatic:
VVCP > VCPUV (rising)
Over Voltage Protection
(OVP)		 VVM > VOVP (rising) OVP_EN = 0b None Active Active No action
OVP_EN = 1b nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Automatic:
VVM < VOVP (falling)
Over Current Protection
(OCP)		 IPHASE > IOCP OCP_MODE = 00b nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
OCP_MODE = 01b nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Retry:
tRETRY
Buck Overcurrent Protection
(BUCK_OCP)		 IBK > IBK_OCP — — Hi-Z Disabled Automatic
Motor Lock
(MTR_LCK )		 Motor lock: Abnormal Speed; No Motor Lock; Abnormal BEMF MTR_LCK_MODE = 000b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MTR_LCK_MODE = 001b nFAULT and CONTROLLER_FAULT_STATUS register Low- side brake Active Latched:
CLR_FLT
MTR_LCK_MODE = 010b nFAULT and CONTROLLER_FAULT_STATUS register High- side brake Active Latched:
CLR_FLT
MTR_LCK_MODE = 011b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 100b nFAULT and CONTROLLER_FAULT_STATUS register Low- side brake Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 101b nFAULT and CONTROLLER_FAULT_STATUS register High- side brake Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 110b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
MTR_LCK_MODE = 111b None Active Active No action
Hardware Lock-Detection Current Limit
(HW_LOCK_LIMIT)
VSOX > HW_LOCK_ILIMIT HW_LOCK_ILIMIT_MODE = 000b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE = 001b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE = 010b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE = 011b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE = 100b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE = 101b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE= 110b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
HW_LOCK_ILIMIT_MODE = 111b None Active Active No action
Software Lock-Detection Current Limit
(LOCK_LIMIT)
VSOX > LOCK_ILIMIT LOCK_ILIMIT_MODE = 000b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 001b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 010b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 011b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE = 100b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE = 101b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE= 110b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
LOCK_ILIMIT_MODE = 111b None Active Active No action
IPD Timeout Fault
(IPD_T1_FAULT and IPD_T2_FAULT)		 IPD TIME > 500ms (approx.), during IPD current ramp up or ramp down IPD_TIMEOUT_FAULT_EN = 0b — Active Active No action
IPD_TIMEOUT_FAULT_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry: tLCK_RETRY
IPD Frequency Fault
(IPD_FREQ_FAULT)		 IPD pulse before the current decay in previous IPD pulse IPD_FREQ_FAULT_EN = 0b — Active Active No action
IPD_FREQ_FAULT_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry: tLCK_RETRY
MPET IPD Fault
(MPET_IPD_FAULT)		 Same as IPD Timeout Fault during MPET R, L measurement — nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MPET Back-EMF Fault
(MPET_BEMF_FAULT)		 Motor Back EMF < STAT_DETECT_THR during MPET Ke and mechanical parameters measurement — nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
Maximum VM (overvoltage) fault VVM > MAX_VM_MOTOR, if MAX_VM_MOTOR ≠ 000b MAX_VM_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MAX_VM_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Automatic:
(VVM < MAX_VM_MOTOR - VOLTAGE_HYSTERESIS)V
Minimum VM (undervoltage) fault VVM < MIN_VM_MOTOR, if MIN_VM_MOTOR ≠ 000b MIN_VM_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MIN_VM_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Automatic:
(VVM > MIN_VM_MOTOR + VOLTAGE_HYSTERESIS)V
External Watchdog Watchdog tickle does not arrive before configured time interval when EXT_WDT_EN =1b. Refer Section 6.5.5 EXT_WDT_FAULT_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
EXT_WDT_FAULT_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
EEPROM Fault Indicates EEPROM contents error/mismatch; content evaluation happens whenever a EEPROM read is issued EEP_FAULT_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
EEP_FAULT_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
I2C CRC Fault Indicates error in I2C transaction as a CRC mismatch CRC_ERR_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
CRC_ERR_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
Current Loop Saturation Indication of current loop saturation due to lower VVM SATURATION_FLAGS_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active; motor speed may not reach speed reference Active Automatic: motor will reach reference operating point upon exiting saturation
Speed Loop Saturation Indication of speed loop saturation due to lower VVM, lower ILIMIT setting etc., SATURATION_FLAGS_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active; motor speed may not reach speed reference Active Automatic: motor will reach reference operating point upon exiting saturation
Thermal warning
(OTW)		 TJ > TOTW OTW_REP = 0b — Active Active No action
OTW_REP = 1b nFAULT and GATE_DRIVER_FAULT_STATUS register Active Active No action
FET thermal shutdown
(TSD_FET)		 TJ > TTSD_FET — nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Automatic:
TJ < TTSD_FET – TTSD_FET_HYS