SLLSFX9 December   2024 MCF8316D

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Output Stage
      2. 6.3.2  Device Interface
        1. 6.3.2.1 Interface - Control and Monitoring
        2. 6.3.2.2 I2C Interface
      3. 6.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 6.3.3.1 Buck in Inductor Mode
        2. 6.3.3.2 Buck in Resistor mode
        3. 6.3.3.3 Buck Regulator with External LDO
        4. 6.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 6.3.3.5 Mixed Mode Buck Operation and Control
      4. 6.3.4  AVDD Linear Voltage Regulator
      5. 6.3.5  Charge Pump
      6. 6.3.6  Slew Rate Control
      7. 6.3.7  Cross Conduction (Dead Time)
      8. 6.3.8  Motor Control Input Sources
        1. 6.3.8.1 Analog-Mode Motor Control
        2. 6.3.8.2 PWM-Mode Motor Control
        3. 6.3.8.3 I2C-based Motor Control
        4. 6.3.8.4 Frequency-Mode Motor Control
        5. 6.3.8.5 Input Reference Profiles
          1. 6.3.8.5.1 Linear Control Profiles
          2. 6.3.8.5.2 Staircase Control Profiles
          3. 6.3.8.5.3 Forward-Reverse Profiles
          4. 6.3.8.5.4 Multi-Reference Mode Operation
          5. 6.3.8.5.5 Input Reference Transfer Function without Profiler
      9. 6.3.9  Starting the Motor Under Different Initial Conditions
        1. 6.3.9.1 Case 1 – Motor is Stationary
        2. 6.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 6.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 6.3.10 Motor Start Sequence (MSS)
        1. 6.3.10.1 Initial Speed Detect (ISD)
        2. 6.3.10.2 Motor Resynchronization
        3. 6.3.10.3 Reverse Drive
          1. 6.3.10.3.1 Reverse Drive Tuning
        4. 6.3.10.4 Motor Start-up
          1. 6.3.10.4.1 Align
          2. 6.3.10.4.2 Double Align
          3. 6.3.10.4.3 Initial Position Detection (IPD)
            1. 6.3.10.4.3.1 IPD Operation
            2. 6.3.10.4.3.2 IPD Release Mode
            3. 6.3.10.4.3.3 IPD Advance Angle
          4. 6.3.10.4.4 Slow First Cycle Startup
          5. 6.3.10.4.5 Open Loop
          6. 6.3.10.4.6 Transition from Open to Closed Loop
      11. 6.3.11 Closed Loop Operation
        1. 6.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 6.3.11.2 Speed PI Control
        3. 6.3.11.3 Current PI Control
        4. 6.3.11.4 Power Control Mode
        5. 6.3.11.5 Current (Torque) Control Mode
        6. 6.3.11.6 Modulation Index Control
        7. 6.3.11.7 Overmodulation
        8. 6.3.11.8 Motor Speed Limit
        9. 6.3.11.9 Input DC Power Limit
      12. 6.3.12 Flux Weakening Control
      13. 6.3.13 Motor Parameters
        1. 6.3.13.1 Motor Resistance
        2. 6.3.13.2 Motor Inductance
        3. 6.3.13.3 Motor Back-EMF constant
      14. 6.3.14 Motor Parameter Extraction Tool (MPET)
      15. 6.3.15 Anti-Voltage Surge (AVS)
      16. 6.3.16 Active Braking
      17. 6.3.17 Output PWM Switching Frequency
      18. 6.3.18 PWM Dithering
      19. 6.3.19 PWM Modulation Schemes
      20. 6.3.20 Dead Time Compensation
      21. 6.3.21 Motor Stop Options
        1. 6.3.21.1 Coast (Hi-Z) Mode
        2. 6.3.21.2 Recirculation Mode
        3. 6.3.21.3 Low-Side Braking
        4. 6.3.21.4 High-Side Braking
        5. 6.3.21.5 Active Spin-Down
      22. 6.3.22 Align Braking
      23. 6.3.23 FG Configuration
        1. 6.3.23.1 FG Output Frequency
        2. 6.3.23.2 FG during Open and Closed Loop States
        3. 6.3.23.3 FG during Fault and Idle States
      24. 6.3.24 Protections
        1. 6.3.24.1  VM Supply Undervoltage Lockout
        2. 6.3.24.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 6.3.24.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 6.3.24.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 6.3.24.5  Overvoltage Protection (OVP)
        6. 6.3.24.6  Overcurrent Protection (OCP)
          1. 6.3.24.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 6.3.24.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 6.3.24.7  Buck Overcurrent Protection
        8. 6.3.24.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 6.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown
          2. 6.3.24.8.2 HW_LOCK_ILIMIT Automatic Recovery
          3. 6.3.24.8.3 HW_LOCK_ILIMIT Report Only
          4. 6.3.24.8.4 HW_LOCK_ILIMIT Disabled
        9. 6.3.24.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 6.3.24.9.1 LOCK_ILIMIT Latched Shutdown
          2. 6.3.24.9.2 LOCK_ILIMIT Automatic Recovery
          3. 6.3.24.9.3 LOCK_ILIMIT Report Only
          4. 6.3.24.9.4 LOCK_ILIMIT Disabled
        10. 6.3.24.10 Motor Lock Detection
          1. 6.3.24.10.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 6.3.24.10.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 6.3.24.10.3 Lock3: No-Motor Fault (NO_MTR)
        11. 6.3.24.11 Motor Lock (MTR_LCK)
          1. 6.3.24.11.1 MTR_LCK Latched Shutdown
          2. 6.3.24.11.2 MTR_LCK Automatic Recovery
          3. 6.3.24.11.3 MTR_LCK Report Only
          4. 6.3.24.11.4 MTR_LCK Disabled
        12. 6.3.24.12 EEPROM Fault
        13. 6.3.24.13 I2C CRC Fault
        14. 6.3.24.14 Minimum VM (Undervoltage) Protection
        15. 6.3.24.15 Maximum VM (Overvoltage) Protection
        16. 6.3.24.16 MPET Faults
        17. 6.3.24.17 IPD Faults
        18. 6.3.24.18 FET Thermal Warning (OTW)
        19. 6.3.24.19 FET Thermal Shutdown (TSD_FET)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Standby Mode
        3. 6.4.1.3 Fault Reset (CLR_FLT)
    5. 6.5 External Interface
      1. 6.5.1 DRVOFF Functionality
      2. 6.5.2 DAC outputs
      3. 6.5.3 Current Sense Output
      4. 6.5.4 Oscillator Source
        1. 6.5.4.1 External Clock Source
      5. 6.5.5 External Watchdog
    6. 6.6 EEPROM access and I2C interface
      1. 6.6.1 EEPROM Access
        1. 6.6.1.1 EEPROM Write
        2. 6.6.1.2 EEPROM Read
        3. 6.6.1.3 EEPROM Security
      2. 6.6.2 I2C Serial Interface
        1. 6.6.2.1 I2C Data Word
        2. 6.6.2.2 I2C Write Transaction
        3. 6.6.2.3 I2C Read Transaction
        4. 6.6.2.4 I2C Communication Protocol Packet Examples
        5. 6.6.2.5 I2C Clock Stretching
        6. 6.6.2.6 CRC Byte Calculation
    7. 6.7 EEPROM (Non-Volatile) Register Map
      1. 6.7.1 Algorithm_Configuration Registers
      2. 6.7.2 Fault_Configuration Registers
      3. 6.7.3 Hardware_Configuration Registers
      4. 6.7.4 Internal_Algorithm_Configuration Registers
    8. 6.8 RAM (Volatile) Register Map
      1. 6.8.1 Fault_Status Registers
      2. 6.8.2 System_Status Registers
      3. 6.8.3 Device_Control Registers
      4. 6.8.4 Algorithm_Control Registers
      5. 6.8.5 Algorithm_Variables Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Application Curves
        1. 7.2.1.1 Motor startup
        2. 7.2.1.2 MPET
        3. 7.2.1.3 Dead time compensation
        4. 7.2.1.4 Auto handoff
        5. 7.2.1.5 Anti voltage surge (AVS)
        6. 7.2.1.6 Real time variable tracking using DACOUT
  9. 8 Power Supply Recommendations
    1. 8.1 Bulk Capacitance
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
      1. 9.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Support Resources
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

6.3.1 Output Stage

The MCF8316D consists of integrated 95mΩ (combined high-side and low-side FETs' on-state resistance) NMOS FETs connected in a three-phase bridge configuration. A doubler charge pump provides the proper gate-bias voltage to the high-side NMOS FETs across a wide operating voltage range in addition to providing 100% duty-cycle support. An internal linear regulator provides the gate-bias voltage for the low-side MOSFETs.