SLLSFX9 December   2024 MCF8316D

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Output Stage
      2. 6.3.2  Device Interface
        1. 6.3.2.1 Interface - Control and Monitoring
        2. 6.3.2.2 I2C Interface
      3. 6.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 6.3.3.1 Buck in Inductor Mode
        2. 6.3.3.2 Buck in Resistor mode
        3. 6.3.3.3 Buck Regulator with External LDO
        4. 6.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 6.3.3.5 Mixed Mode Buck Operation and Control
      4. 6.3.4  AVDD Linear Voltage Regulator
      5. 6.3.5  Charge Pump
      6. 6.3.6  Slew Rate Control
      7. 6.3.7  Cross Conduction (Dead Time)
      8. 6.3.8  Motor Control Input Sources
        1. 6.3.8.1 Analog-Mode Motor Control
        2. 6.3.8.2 PWM-Mode Motor Control
        3. 6.3.8.3 I2C-based Motor Control
        4. 6.3.8.4 Frequency-Mode Motor Control
        5. 6.3.8.5 Input Reference Profiles
          1. 6.3.8.5.1 Linear Control Profiles
          2. 6.3.8.5.2 Staircase Control Profiles
          3. 6.3.8.5.3 Forward-Reverse Profiles
          4. 6.3.8.5.4 Multi-Reference Mode Operation
          5. 6.3.8.5.5 Input Reference Transfer Function without Profiler
      9. 6.3.9  Starting the Motor Under Different Initial Conditions
        1. 6.3.9.1 Case 1 – Motor is Stationary
        2. 6.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 6.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 6.3.10 Motor Start Sequence (MSS)
        1. 6.3.10.1 Initial Speed Detect (ISD)
        2. 6.3.10.2 Motor Resynchronization
        3. 6.3.10.3 Reverse Drive
          1. 6.3.10.3.1 Reverse Drive Tuning
        4. 6.3.10.4 Motor Start-up
          1. 6.3.10.4.1 Align
          2. 6.3.10.4.2 Double Align
          3. 6.3.10.4.3 Initial Position Detection (IPD)
            1. 6.3.10.4.3.1 IPD Operation
            2. 6.3.10.4.3.2 IPD Release Mode
            3. 6.3.10.4.3.3 IPD Advance Angle
          4. 6.3.10.4.4 Slow First Cycle Startup
          5. 6.3.10.4.5 Open Loop
          6. 6.3.10.4.6 Transition from Open to Closed Loop
      11. 6.3.11 Closed Loop Operation
        1. 6.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 6.3.11.2 Speed PI Control
        3. 6.3.11.3 Current PI Control
        4. 6.3.11.4 Power Control Mode
        5. 6.3.11.5 Current (Torque) Control Mode
        6. 6.3.11.6 Modulation Index Control
        7. 6.3.11.7 Overmodulation
        8. 6.3.11.8 Motor Speed Limit
        9. 6.3.11.9 Input DC Power Limit
      12. 6.3.12 Flux Weakening Control
      13. 6.3.13 Motor Parameters
        1. 6.3.13.1 Motor Resistance
        2. 6.3.13.2 Motor Inductance
        3. 6.3.13.3 Motor Back-EMF constant
      14. 6.3.14 Motor Parameter Extraction Tool (MPET)
      15. 6.3.15 Anti-Voltage Surge (AVS)
      16. 6.3.16 Active Braking
      17. 6.3.17 Output PWM Switching Frequency
      18. 6.3.18 PWM Dithering
      19. 6.3.19 PWM Modulation Schemes
      20. 6.3.20 Dead Time Compensation
      21. 6.3.21 Motor Stop Options
        1. 6.3.21.1 Coast (Hi-Z) Mode
        2. 6.3.21.2 Recirculation Mode
        3. 6.3.21.3 Low-Side Braking
        4. 6.3.21.4 High-Side Braking
        5. 6.3.21.5 Active Spin-Down
      22. 6.3.22 Align Braking
      23. 6.3.23 FG Configuration
        1. 6.3.23.1 FG Output Frequency
        2. 6.3.23.2 FG during Open and Closed Loop States
        3. 6.3.23.3 FG during Fault and Idle States
      24. 6.3.24 Protections
        1. 6.3.24.1  VM Supply Undervoltage Lockout
        2. 6.3.24.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 6.3.24.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 6.3.24.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 6.3.24.5  Overvoltage Protection (OVP)
        6. 6.3.24.6  Overcurrent Protection (OCP)
          1. 6.3.24.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 6.3.24.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 6.3.24.7  Buck Overcurrent Protection
        8. 6.3.24.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 6.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown
          2. 6.3.24.8.2 HW_LOCK_ILIMIT Automatic Recovery
          3. 6.3.24.8.3 HW_LOCK_ILIMIT Report Only
          4. 6.3.24.8.4 HW_LOCK_ILIMIT Disabled
        9. 6.3.24.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 6.3.24.9.1 LOCK_ILIMIT Latched Shutdown
          2. 6.3.24.9.2 LOCK_ILIMIT Automatic Recovery
          3. 6.3.24.9.3 LOCK_ILIMIT Report Only
          4. 6.3.24.9.4 LOCK_ILIMIT Disabled
        10. 6.3.24.10 Motor Lock Detection
          1. 6.3.24.10.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 6.3.24.10.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 6.3.24.10.3 Lock3: No-Motor Fault (NO_MTR)
        11. 6.3.24.11 Motor Lock (MTR_LCK)
          1. 6.3.24.11.1 MTR_LCK Latched Shutdown
          2. 6.3.24.11.2 MTR_LCK Automatic Recovery
          3. 6.3.24.11.3 MTR_LCK Report Only
          4. 6.3.24.11.4 MTR_LCK Disabled
        12. 6.3.24.12 EEPROM Fault
        13. 6.3.24.13 I2C CRC Fault
        14. 6.3.24.14 Minimum VM (Undervoltage) Protection
        15. 6.3.24.15 Maximum VM (Overvoltage) Protection
        16. 6.3.24.16 MPET Faults
        17. 6.3.24.17 IPD Faults
        18. 6.3.24.18 FET Thermal Warning (OTW)
        19. 6.3.24.19 FET Thermal Shutdown (TSD_FET)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Standby Mode
        3. 6.4.1.3 Fault Reset (CLR_FLT)
    5. 6.5 External Interface
      1. 6.5.1 DRVOFF Functionality
      2. 6.5.2 DAC outputs
      3. 6.5.3 Current Sense Output
      4. 6.5.4 Oscillator Source
        1. 6.5.4.1 External Clock Source
      5. 6.5.5 External Watchdog
    6. 6.6 EEPROM access and I2C interface
      1. 6.6.1 EEPROM Access
        1. 6.6.1.1 EEPROM Write
        2. 6.6.1.2 EEPROM Read
        3. 6.6.1.3 EEPROM Security
      2. 6.6.2 I2C Serial Interface
        1. 6.6.2.1 I2C Data Word
        2. 6.6.2.2 I2C Write Transaction
        3. 6.6.2.3 I2C Read Transaction
        4. 6.6.2.4 I2C Communication Protocol Packet Examples
        5. 6.6.2.5 I2C Clock Stretching
        6. 6.6.2.6 CRC Byte Calculation
    7. 6.7 EEPROM (Non-Volatile) Register Map
      1. 6.7.1 Algorithm_Configuration Registers
      2. 6.7.2 Fault_Configuration Registers
      3. 6.7.3 Hardware_Configuration Registers
      4. 6.7.4 Internal_Algorithm_Configuration Registers
    8. 6.8 RAM (Volatile) Register Map
      1. 6.8.1 Fault_Status Registers
      2. 6.8.2 System_Status Registers
      3. 6.8.3 Device_Control Registers
      4. 6.8.4 Algorithm_Control Registers
      5. 6.8.5 Algorithm_Variables Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Application Curves
        1. 7.2.1.1 Motor startup
        2. 7.2.1.2 MPET
        3. 7.2.1.3 Dead time compensation
        4. 7.2.1.4 Auto handoff
        5. 7.2.1.5 Anti voltage surge (AVS)
        6. 7.2.1.6 Real time variable tracking using DACOUT
  9. 8 Power Supply Recommendations
    1. 8.1 Bulk Capacitance
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
      1. 9.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Support Resources
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

5.5 Electrical Characteristics

at TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES
IVMQVM sleep mode currentVVM > 6 V, VSPEED = 0, TA = 25 °C35µA
VSPEED = 0, TA = 125 °C3.57µA
IVMSVM standby mode currentVVM > 6 V, VSPEED > VEN_SB, DRVOFF = High, TA = 25 °C, LBK = 47 µH, CBK = 22 µF 815mA
VVM > 6 V, VSPEED > VEN_SB, DRVOFF = High, RBK = 22 Ω, CBK = 22 µF2528mA
VVM > 6 V, VSPEED > VEN_SB, DRVOFF = High, LBK = 47 µH, CBK = 22 µF 815mA
VVM > 6 V, VSPEED > VEN_SB, DRVOFF = High, RBK = 22 Ω, CBK = 22 µF2528mA
IVMVM operating mode currentVVM > 6 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 0011b (25 kHz), TJ = 25 °C, LBK = 47 µH, CBK = 22 µF, No Motor Connected1118mA
VVM > 6 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 0011b (25 kHz), TJ = 25 °C, RBK = 22 Ω, CBK = 22 µF, No Motor Connected2732mA
VVM > 6 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 0011b (25 kHz), LBK = 47 µH, CBK = 22 µF, No Motor Connected1117mA
VVM > 6 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 0011b (25 kHz), RBK = 22 Ω, CBK = 22 µF, No Motor Connected2833mA
VAVDDAnalog regulator voltage0 mA ≤ IAVDD ≤ 20 mA3.1253.33.465V
IAVDDExternal analog regulator load20mA
VDVDDDigital regulator voltage1.41.551.65V
VVCPCharge pump regulator voltageVCP with respect to VM4.04.75.5V
BUCK REGULATOR
VBKBuck regulator average voltage
(LBK = 47 µH, CBK = 22 µF)
 		VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 00b3.13.33.5V
VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 01b4.65.05.4V
VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 10b3.74.04.3V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 11b5.25.75.8V
VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b, 11b), 0 mA ≤ IBK ≤ 170 mAVVM–IBK*(RLBK+2) 1V
VBKBuck regulator average voltage
(LBK = 22 µH, CBK = 22 µF)
 		VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 00b3.13.33.5V
VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 01b4.65.05.4V
VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 10b3.74.04.3V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 11b5.25.75.8V
VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b, 11b), 0 mA ≤ IBK ≤ 20 mAVVM–IBK*(RLBK+2)1V
VBKBuck regulator average voltage
(RBK = 22 Ω, CBK = 22 µF)
 		VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 00b3.13.33.5V
VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 01b4.65.05.4V
VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 10b3.74.04.3V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 11b5.25.75.8V
VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b, 11b), 0 mA ≤ IBK ≤ 10 mAVVM–IBK*(RLBK+2) (1)V
VBK_RIPBuck regulator ripple voltageVVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, Buck regulator with inductor, LBK = 47 µH, CBK = 22 µF–100100mV
VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, Buck regulator with inductor, LBK = 22 µH, CBK = 22 µF–100100mV
VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, Buck regulator with resistor, RBK = 22 Ω, CBK = 22 µF–100100mV
IBKExternal buck regulator loadLBK = 47 µH, CBK = 22 µF, BUCK_PS_DIS = 1b170mA
LBK = 47 µH, CBK = 22 µF, BUCK_PS_DIS = 0b170 – IAVDDmA
LBK = 22 µH, CBK = 22 µF, BUCK_PS_DIS = 1b20mA
LBK = 22 µH, CBK = 22 µF, BUCK_PS_DIS = 0b20 – IAVDDmA
RBK = 22 Ω, CBK = 22 µF, BUCK_PS_DIS = 1b10mA
RBK = 22 Ω, CBK = 22 µF, BUCK_PS_DIS = 0b10 – IAVDDmA
fSW_BKBuck regulator switching frequencyRegulation Mode20535kHz
Linear Mode20535kHz
VBK_UVBuck regulator undervoltage lockout
 		VBK rising, BUCK_SEL = 00b2.72.82.95V
VBK falling, BUCK_SEL = 00b2.52.62.7V
VBK rising, BUCK_SEL = 01b4.34.44.55V
VBK falling, BUCK_SEL = 01b4.14.24.38V
VBK rising, BUCK_SEL = 10b2.72.82.95V
VBK falling, BUCK_SEL = 10b2.52.62.7V
VBK rising, BUCK_SEL = 11b4.34.44.55V
VBK falling, BUCK_SEL = 11b4.14.24.38V
VBK_UV_HYSBuck regulator undervoltage lockout hysteresisRising to falling threshold, BUCK_SEL = 00b90200400mV
Rising to falling threshold, BUCK_SEL = 01b90200400mV
Rising to falling threshold, BUCK_SEL = 10b90200400mV
Rising to falling threshold, BUCK_SEL =11b90200400mV
IBK_CLBuck regulator current limit threshold
 		BUCK_CL = 0b360600910mA
BUCK_CL = 1b80150260mA
IBK_OCPBuck regulator overcurrent protection trip point234A
tBK_RETRYOvercurrent protection retry time0.711.3ms
DRIVER OUTPUTS
RDS(ON)Total MOSFET on resistance (High-side + Low-side)VVM > 6 V, IOUT = 1 A, TA = 25°C95125mΩ
VVM < 6 V, IOUT = 1 A, TA = 25°C105130mΩ
VVM > 6 V, IOUT = 1 A, TJ = 150 °C140185mΩ
VVM < 6 V, IOUT = 1 A, TJ = 150 °C145190mΩ
SRPhase pin slew rate switching low to high (Rising from 20 % to 80 %)VVM = 24 V, SLEW_RATE = 10b80125185V/µs
VVM = 24 V, SLEW_RATE = 11b130200280V/µs
SRPhase pin slew rate switching high to low (Falling from 80 % to 20 %VVM = 24 V, SLEW_RATE = 10b80125185V/µs
VVM = 24 V, SLEW_RATE = 11b110200280V/µs
tDEADOutput dead time (high to low / low to high)VVM = 24 V, SLEW_RATE = 10b6501000ns
VVM = 24 V, SLEW_RATE = 11b500750ns
SPEED INPUT - PWM MODE
ƒPWMPWM input frequency0.01100kHz
ResPWMPWM input resolution0.01 kHz ≤ fPWM < 0.35 kHz111213bits
0.35 kHz ≤ fPWM < 2 kHz121314bits
2 kHz ≤ fPWM < 3.5 kHz1111.512bits
3.5 kHz ≤ fPWM < 7 kHz1313.514bits
7 kHz ≤ fPWM < 14 kHz1212.513bits
14 kHz ≤ fPWM < 29.3 kHz 1111.512bits
29.3 kHz ≤ fPWM < 60 kHz1010.511bits
60 kHz ≤ fPWM ≤ 100 kHz8910bits
SPEED INPUT - ANALOG MODE
VANA_FSAnalog full-speed voltage2.9533.05V
VANA_RESAnalog voltage resolution732μV
SPEED INPUT - FREQUENCY MODE
ƒPWM_FREQPWM input frequency range Duty cycle = 50%332767Hz
SLEEP MODE
VEN_SLAnalog voltage to enter sleep stateSPEED_MODE = 00b (analog mode)40mV
VEX_SLAnalog voltage to exit sleep stateSPEED_MODE = 00b (analog mode)2.2V
tDET_ANATime needed to detect wake-up signal on SPEED pin SPEED_MODE = 00b (analog mode)
VSPEED > VEX_SL		0.511.5μs
tWAKEWake-up time from sleep stateVSPEED > VEX_SL to DVDD voltage available, SPEED_MODE = 00b (analog mode)35ms
tEX_SL_DR_ANATime taken to drive motor after wake-up from sleep state (MCF8316D)SPEED_MODE = 00b (analog mode), DVDD voltage available to first output PWM pulse, ISD detection disabled30ms
tEX_SL_DR_ANATime taken to drive motor after wake-up from sleep state (MCF8316DUL)SPEED_MODE = 00b (analog mode), DVDD voltage available to first output PWM pulse, ISD detection disabled180ms
tDET_PWMTime needed to detect wake-up signal on SPEED pin SPEED_MODE = 01b (PWM mode)
VSPEED > VIH		0.511.5μs
tWAKE_PWMWake-up time from sleep stateVSPEED > VIH to DVDD voltage available, SPEED_MODE = 01b (PWM mode)35ms
tEX_SL_DR_PWMTime taken to drive motor after wake-up from sleep state (MCF8316D)SPEED_MODE = 01b (PWM mode), DVDD voltage available to first output PWM pulse, ISD detection disabled30ms
tEX_SL_DR_PWMTime taken to drive motor after wake-up from sleep state (MCF8316DUL)SPEED_MODE = 01b (PWM mode), DVDD voltage available to first output PWM pulse, ISD detection disabled180ms
tDET_SL_ANATime needed to detect sleep commandSPEED_MODE = 00b (analog mode), 
VSPEED < VEN_SL, SLEEP_ENTRY_TIME = 00b		0.0350.050.065ms
SPEED_MODE = 00b (analog mode), 
VSPEED < VEN_SL, SLEEP_ENTRY_TIME = 01b		0.140.20.26ms
SPEED_MODE = 00b (analog mode), 
VSPEED < VEN_SL, SLEEP_ENTRY_TIME = 10b		142026ms
SPEED_MODE = 00b (analog mode), 
VSPEED < VEN_SL, SLEEP_ENTRY_TIME = 11b		140200260ms
tDET_SL_PWMTime needed to detect sleep commandSPEED_MODE = 01b (PWM mode) or 11b (Frequency mode), 
VSPEED < VIL, SLEEP_ENTRY_TIME = 00b		0.0350.050.065ms
SPEED_MODE = 01b (PWM mode) or 11b (Frequency mode), 
VSPEED < VIL, SLEEP_ENTRY_TIME = 01b		0.140.20.26ms
SPEED_MODE = 01b (PWM mode) or 11b (Frequency mode), 
VSPEED < VIL, SLEEP_ENTRY_TIME = 10b		142026ms
SPEED_MODE = 01b (PWM mode) or 11b (Frequency mode), 
VSPEED < VIL, SLEEP_ENTRY_TIME = 11b		140200260ms
tEN_SLTime needed to stop driving motor after detecting sleep commandVSPEED < VEN_SL (analog mode) or VSPEED < VIL (PWM mode or Frequency mode) or VSPEED < VIL and DIGITAL_SPEED_CTRL = 0b (I2C mode)12ms
STANDBY MODE
tEX_SB_DR_ANATime taken to drive motor after exiting standby stateSPEED_MODE = 00b (analog mode)
VSPEED > VEX_SB, ISD detection disabled		6ms
tEX_SB_DR_PWMTime taken to drive motor after exiting standby stateSPEED_MODE = 01b (PWM mode)
VSPEED > VIH, ISD detection disabled		6ms
tDET_SB_ANATime needed to detect standby commandSPEED_MODE = 00b (analog mode)
VSPEED < VEN_SB		0.512ms
tEN_SB_PWMTime needed to detect standby commandSPEED_MODE = 01b (PWM mode)
VSPEED < VIL, SLEEP_ENTRY_TIME = 00b		0.0350.050.065ms
SPEED_MODE = 01b (PWM mode)
VSPEED < VIL, SLEEP_ENTRY_TIME = 01b		0.140.20.26ms
SPEED_MODE = 01b (PWM mode)
VSPEED < VIL, SLEEP_ENTRY_TIME = 10b		142026ms
SPEED_MODE = 01b (PWM mode)
VSPEED < VIL, SLEEP_ENTRY_TIME = 11b		140200260ms
tEN_SB_DIGTime needed to detect standby commandSPEED_MODE = 10b (I2C mode), DIGITAL_SPEED_CTRL = 0b12ms
tEN_SB_FREQTime needed to detect standby commandSPEED_MODE = 11b (Frequency mode), VSPEED < VIL4000ms
tEN_SBTime needed to stop driving motor after detecting standby commandVSPEED < VEN_SL (analog mode) or VSPEED < VIL (PWM or Frequency mode) or DIGITAL_SPEED_CTRL = 0b (I2C mode)12ms
LOGIC-LEVEL INPUTS (BRAKE, DIR, EXT_CLK, EXT_WD, SCL, SDA, SPEED)
VILInput logic low voltageAVDD = 3 to 3.6 V0.25*AVDDV
VIHInput logic high voltageAVDD = 3 to 3.6 V0.65*AVDDV
VHYSInput hysteresis50500800mV
IILInput logic low currentAVDD = 3 to 3.6 V-0.150.15µA
IIHInput logic high currentAVDD  = 3 to 3.6 V-0.40.15µA
RPD_SPEEDInput pulldown resistanceSPEED pin To GND0.611.4MΩ
OPEN-DRAIN OUTPUTS (nFAULT, FG)
VOLOutput logic low voltageIOD =-5 mA0.4V
IOZOutput logic high currentVOD = 3.3 V00.5µA
I2C Serial Interface
VI2C_LLOW-level input voltage -0.50.3*AVDDV
VI2C_HHIGH-level input voltage 0.7*AVDD5.5V
VI2C_HYSHysteresis 0.05*AVDDV
VI2C_OLLOW-level output voltageopen-drain at 2mA sink current 00.4V
II2C_OLLOW-level output currentVI2C_OL = 0.6V6mA
II2C_ILInput current on SDA and SCL-102102µA
CiCapacitance for SDA and SCL10pF
tofOutput fall time from VI2C_H(min) to VI2C_L(max)Standard Mode2503ns
Fast Mode2503ns
tSPPulse width of spikes that must be suppressed by the input filterFast Mode0504ns
OSCILLATOR
fOSCREFExternal clock referenceEXT_CLK_CONFIG = 000b8kHz
EXT_CLK_CONFIG = 001b16kHz
EXT_CLK_CONFIG = 010b32kHz
EXT_CLK_CONFIG = 011b64kHz
EXT_CLK_CONFIG = 100b128kHz
EXT_CLK_CONFIG = 101b256kHz
EXT_CLK_CONFIG = 110b512kHz
EXT_CLK_CONFIG = 111b1024kHz
EEPROM
EEProgProgramming voltage1.351.51.65V
EERETRetentionTA = 25 ℃100Years
TJ = -40 to 150 ℃10Years
EEENDEnduranceTJ = -40 to 150 ℃1000Cycles
TJ = -40 to 85 ℃20000Cycles
PROTECTION CIRCUITS
VUVLOSupply undervoltage lockout (UVLO)VM rising4.34.44.5V
VM falling4.14.24.3V
VUVLO_HYSSupply undervoltage lockout hysteresisRising to falling threshold110200350mV
tUVLOSupply undervoltage deglitch time357µs
VOVPSupply overvoltage protection (OVP)Supply rising, OVP_EN = 1, OVP_SEL = 032.53435V
Supply falling, OVP_EN = 1, OVP_SEL = 031.83334.3V
Supply rising, OVP_EN = 1, OVP_SEL = 1202223V
Supply falling, OVP_EN = 1, OVP_SEL = 1192122V
VOVP_HYSSupply overvoltage protection (OVP)Rising to falling threshold, OVP_SEL = 10.911.1V
Rising to falling threshold, OVP_SEL = 00.70.80.9V
tOVPSupply overvoltage deglitch time2.557µs
VCPUVCharge pump undervoltage lockout (above VM)Supply rising2.252.52.75V
Supply falling2.22.42.6V
VCPUV_HYSCharge pump UVLO hysteresisRising to falling threshold65100150mV
VAVDD_UVAnalog regulator undervoltage lockoutSupply rising2.72.853V
Supply falling2.52.652.8V
VAVDD_UV_HYSAnalog regulator undervoltage lockout hysteresisRising to falling threshold180200240mV
IOCPOvercurrent protection trip pointOCP_LVL = 0b9.51622A
OCP_LVL = 1b152428A
tOCPOvercurrent protection deglitch timeOCP_DEG = 00b0.020.20.4µs
OCP_DEG = 01b0.20.61.2µs
OCP_DEG = 10b0.51.21.8µs
OCP_DEG = 11b0.91.62.5µs
tRETRYOvercurrent protection retry time425500575ms
TOTWThermal warning temperatureDie temperature (TJ)135145155°C
TOTW_HYSThermal warning hysteresisDie temperature (TJ)152025°C
TTSD_BUCKThermal shutdown temperature (Buck)Die temperature (TJ)170180190°C
TTSD_BUCK_HYSThermal shutdown hysteresis (Buck)Die temperature (TJ)152025°C
TTSD_FETThermal shutdown temperature (FET)Die temperature (TJ)165175185°C
TTSD_FET_HYSThermal shutdown hysteresis (FET)Die temperature (TJ)202530°C
(1) RLBK is the resistance of inductor LBK
(2) If AVDD is switched off, I/O pins must not obstruct the SDA and SCL lines.
(3) The maximum tf for the SDA and SCL bus lines (300ns) is longer than the specified maximum tof for the output stages (250ns). This allows series protection resistors (Rs) to connect the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
(4) Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns