JAJSMU9B August 2021 – February 2022 MCT8316A
PRODUCTION DATA
PIN | 40-pin Package | TYPE(1) | DESCRIPTION | |
---|---|---|---|---|
NAME | MCT8316AV | MCT8316AT | ||
AGND | 26 | 26 | GND | Device analog ground. Refer Section 11.1 for connections recommendation. |
AVDD | 27 | 27 | PWR O | 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the AVDD1 and AGND pins. This regulator can source up to 20 mA externally. |
BRAKE | 35 | 35 | I | High → brake the
motor Low → normal operation Connect to PGND via 10-kΩ resistor, if not used |
CONFIG_1 | - | 33 | I | Connect resistor to GND for parameter configuration. |
CONFIG_2 | - | 37 | I | Connect resistor to GND for parameter configuration. |
CONFIG_3 | - | 38 | I | Connect resistor to GND for parameter configuration. |
CP | 8 | 8 | PWR | Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the CP and VM pins. |
CPH | 7 | 7 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device. |
CPL | 6 | 6 | PWR | |
DACOUT2/SOX | 36 | - | O | Multipurpose pin: DAC output when configured as DACOUT2 CSA output configured as SOX |
DACOUT1 | 37 | - | O | DAC output DACOUT1 |
DACOUT2 | 38 | - | O | DAC output DACOUT2 |
DGND | 2 | 2 | GND | Device digital ground. Refer Section 11.1 for connections recommendation. |
DIR | 34 | 34 | I | Direction of motor
spinning; When low, phase driving sequence is OUT A → OUT B → OUT C When high, phase driving sequence is OUT A → OUT C → OUT B Connect to PGND via 10-kΩ resistor, if not used |
DRVOFF | 21 | 21 | I | Coast (Hi-Z) all six MOSFETs. |
DVDD | 1 | 1 | PWR | 1.5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. |
EXT_CLK | 33 | - | I | External clock reference input in external clock reference mode. |
EXT_WD | 32 | - | I | External watchdog input. |
FB_BK | 3 | 3 | PWR I/O | Feedback for buck regulator. Connect to buck regulator output after the inductor/resistor. |
FG | 29 | 29 | O | Motor speed indicator output. Open-drain output requires an external pull-up resistor to 1.8 to 5-V. |
GND_BK | 4 | 4 | GND | Buck regulator ground. Refer Section 11.1 for connections recommendation. |
ILIMIT | - | 39 | I | Connect resistor to GND for parameter configuration. |
LDANGLE | - | 32 | I | Connect resistor to GND for parameter configuration. |
NC | 22, 23, 24, 25, 39 | 22, 23, 24, 25 | - | No connection, open |
nFAULT | 40 | 40 | O | Fault indicator. Pulled logic-low with fault condition; Open-drain output requires an external pull-up resistor to 1.8V to 5.0V. |
OUTA | 13, 14 | 13, 14 | PWR O | Half bridge output A |
OUTB | 16, 17 | 16, 17 | PWR O | Half bridge output B |
OUTC | 19, 20 | 19, 20 | PWR O | Half bridge output C |
PGND | 12, 15, 18 | 12, 15, 18 | GND | Device power ground. Refer Section 11.1 for connections recommendation. |
RMP_1 | - | 30 | I | Connect resistor to GND for parameter configuration. |
RMP_2 | - | 31 | I | Connect resistor to GND for parameter configuration. |
SCL | 31 | - | I | I2C clock input |
SDA | 30 | - | I/O | I2C data line |
SLEW_RATE | - | 36 | I | Connect resistor to GND for parameter configuration. |
SPEED/WAKE | 28 | 28 | I | Device speed input; supports analog, frequency or PWM speed input. The speed pin input can be configured through SPD_CTRL_MODE. |
SW_BK | 5 | 5 | PWR | Buck switch node. Connect this pin to an inductor or resistor. |
VM | 9, 10, 11 | 9, 10, 11 | PWR I | Device and motor power supply. Connect to motor supply voltage; bypass to GND with a 0.1-µF capacitor plus one bulk capacitor. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device. |
Thermal pad | GND | Must be connected to ground |