SLAS703C April 2010 – September 2020 MSP430BT5190
PRODUCTION DATA
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support multiple capture/compare registers, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
INPUT PIN NUMBER | DEVICE INPUT SIGNAL | MODULE INPUT SIGNAL | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL | OUTPUT PIN NUMBER |
---|---|---|---|---|---|---|
PZ, ZQW | PZ, ZQW | |||||
25, M1-P2.0 | TA1CLK | TACLK | Timer | NA | NA | |
ACLK | ACLK | |||||
SMCLK | SMCLK | |||||
25, M1-P2.0 | TA1CLK | TACLK | ||||
26, L2-P2.1 | TA1.0 | CCI0A | CCR0 | TA0 | TA1.0 | 26, L2-P2.1 |
65, F11-P8.5 | TA1.0 | CCI0B | 65, F11-P8.5 | |||
DVSS | GND | |||||
DVCC | VCC | |||||
27, M2-P2.2 | TA1.1 | CCI1A | CCR1 | TA1 | TA1.1 | 27, M2-P2.2 |
66, E11-P8.6 | TA1.1 | CCI1B | 66, E11-P8.6 | |||
DVSS | GND | |||||
DVCC | VCC | |||||
28, L3-P2.3 | TA1.2 | CCI2A | CCR2 | TA2 | TA1.2 | 28, L3-P2.3 |
56, J12-P7.3 | TA1.2 | CCI2B | 56, J12-P7.3 | |||
DVSS | GND | |||||
DVCC | VCC |