SLAS703C April   2010  – September 2020 MSP430BT5190

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Functional Block Diagram
  5. 5Revision History
  6. 6Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
      1. 6.2.1 Terminal Functions
  7. 7Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 7.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 7.6  Thermal Characteristics
    7. 7.7  Schmitt-Trigger Inputs – General-Purpose I/O
    8. 7.8  Inputs – Ports P1 and P2
    9. 7.9  Leakage Current – General-Purpose I/O
    10. 7.10 Outputs – General-Purpose I/O (Full Drive Strength)
    11. 7.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
    12. 7.12 Output Frequency – General-Purpose I/O
    13. 7.13 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    14. 7.14 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    15. 7.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 7.16 Crystal Oscillator, XT1, High-Frequency Mode
    17. 7.17 Crystal Oscillator, XT2
    18. 7.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 7.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 7.20 DCO Frequency
    21. 7.21 PMM, Brown-Out Reset (BOR)
    22. 7.22 PMM, Core Voltage
    23. 7.23 PMM, SVS High Side
    24. 7.24 PMM, SVM High Side
    25. 7.25 PMM, SVS Low Side
    26. 7.26 PMM, SVM Low Side
    27. 7.27 Wake-up Times From Low-Power Modes and Reset
    28. 7.28 Timer_A
    29. 7.29 Timer_B
    30. 7.30 USCI (UART Mode), Recommended Operating Conditions
    31. 7.31 USCI (UART Mode)
    32. 7.32 USCI (SPI Master Mode), Recommended Operating Conditions
    33. 7.33 USCI (SPI Master Mode)
    34. 7.34 USCI (SPI Slave Mode)
    35. 7.35 USCI (I2C Mode)
    36. 7.36 12-Bit ADC, Power Supply and Input Range Conditions
    37. 7.37 12-Bit ADC, Timing Parameters
    38. 7.38 12-Bit ADC, Linearity Parameters
    39. 7.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 7.40 REF, External Reference
    41. 7.41 REF, Built-In Reference
    42. 7.42 Flash Memory
    43. 7.43 JTAG and Spy-Bi-Wire Interface
  8. 8Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
    3. 8.3  Interrupt Vector Addresses
    4. 8.4  Memory Organization
    5. 8.5  Bootstrap Loader (BSL)
    6. 8.6  JTAG Operation
      1. 8.6.1 JTAG Standard Interface
      2. 8.6.2 Spy-Bi-Wire Interface
    7. 8.7  Flash Memory
    8. 8.8  RAM
    9. 8.9  Peripherals
      1. 8.9.1  Digital I/O
      2. 8.9.2  Oscillator and System Clock
      3. 8.9.3  Power-Management Module (PMM)
      4. 8.9.4  Hardware Multiplier (MPY)
      5. 8.9.5  Real-Time Clock (RTC_A)
      6. 8.9.6  Watchdog Timer (WDT_A)
      7. 8.9.7  System Module (SYS)
      8. 8.9.8  DMA Controller
      9. 8.9.9  Universal Serial Communication Interface (USCI)
      10. 8.9.10 TA0
      11. 8.9.11 TA1
      12. 8.9.12 TB0
      13. 8.9.13 ADC12_A
      14. 8.9.14 CRC16
      15. 8.9.15 REF Voltage Reference
      16. 8.9.16 Embedded Emulation Module (EEM) (L Version)
      17. 8.9.17 Peripheral File Map
    10. 8.10 Input/Output Schematics
      1. 8.10.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 8.10.2  Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 8.10.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
      4. 8.10.4  Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 8.10.5  Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 8.10.6  Port P5, P5.2, Input/Output With Schmitt Trigger
      7. 8.10.7  Port P5, P5.3, Input/Output With Schmitt Trigger
      8. 8.10.8  Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
      9. 8.10.9  Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      10. 8.10.10 Port P7, P7.0, Input/Output With Schmitt Trigger
      11. 8.10.11 Port P7, P7.1, Input/Output With Schmitt Trigger
      12. 8.10.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
      13. 8.10.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      14. 8.10.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      15. 8.10.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      16. 8.10.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
      17. 8.10.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
      18. 8.10.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      19. 8.10.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 8.11 Device Descriptors (TLV)
  9. 9Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Getting Started and Next Steps
      2. 9.1.2 Development Tools Support
        1. 9.1.2.1 Hardware Features
        2. 9.1.2.2 Recommended Hardware Options
          1. 9.1.2.2.1 Experimenter Boards
          2. 9.1.2.2.2 Debugging and Programming Tools
          3. 9.1.2.2.3 Production Programmers
        3. 9.1.2.3 Recommended Software Options
          1. 9.1.2.3.1 Integrated Development Environments
          2. 9.1.2.3.2 MSP430Ware
          3. 9.1.2.3.3 TI-RTOS
          4. 9.1.2.3.4 Command-Line Programmer
      3. 9.1.3 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Export Control Notice
    7. 9.7 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.11 Device Descriptors (TLV)

Table 8-59 shows the complete contents of the device descriptor tag-length-value (TLV) structure.

Table 8-59 Device Descriptor Table
DESCRIPTIONADDRESSSIZE
(bytes)		MSP430BT5190
VALUE
Info BlockInfo length01A00h106h
CRC length01A01h106h
CRC value01A02h2per unit
Device ID01A04h105h
Device ID01A05h180h
Hardware revision01A06h1per unit
Firmware revision01A07h1per unit
Die RecordDie Record Tag01A08h108h
Die Record length01A09h10Ah
Lot/Wafer ID01A0Ah4per unit
Die X position01A0Eh2per unit
Die Y position01A10h2per unit
Test results01A12h2per unit
ADC12 CalibrationADC12 Calibration Tag01A14h111h
ADC12 Calibration length01A15h110h
ADC Gain Factor01A16h2per unit
ADC Offset01A18h2per unit
ADC 1.5-V Reference
Temp. Sensor 30°C		01A1Ah2per unit
ADC 1.5-V Reference
Temp. Sensor 85°C		01A1Ch2per unit
ADC 2.0-V Reference
Temp. Sensor 30°C		01A1Eh2per unit
ADC 2.0-V Reference
Temp. Sensor 85°C		01A20h2per unit
ADC 2.5-V Reference
Temp. Sensor 30°C		01A22h2per unit
ADC 2.5-V Reference
Temp. Sensor 85°C		01A24h2per unit
REF CalibrationREF Calibration Tag01A26h112h
REF Calibration length01A27h106h
REF 1.5-V Reference01A28h2per unit
REF 2.0-V Reference01A2Ah2per unit
REF 2.5-V Reference01A2Ch2per unit
Peripheral DescriptorPeripheral Descriptor Tag01A2Eh102h
Peripheral Descriptor Length01A2Fh161h
Memory 1208h
8Ah
Memory 220Ch
86h
Memory 320Eh
30h
Memory 422Eh
98h
Memory 50/1NA
Delimiter100h
Peripheral count121h
MSP430CPUXV2200h
23h
SBW200h
0Fh
EEM-8200h
05h
TI BSL200h
FCh
Package200h
1Fh
SFR210h
41h
PMM202h
30h
FCTL202h
38h
CRC16-straight201h
3Ch
CRC16-bit reversed200h
3Dh
RAMCTL200h
44h
WDT_A200h
40h
UCS201h
48h
SYS202h
42h
REF203h
A0h
Port 1/2205h
51h
Port 3/4202h
52h
Port 5/6202h
53h
Port 7/8202h
54h
Port 9/10202h
55h
Port 11/12202h
56h
JTAG208h
5Fh
TA0202h
62h
TA1204h
61h
TB0204h
67h
RTC20Eh
68h
MPY32202h
85h
DMA-3204h
47h
USCI_A/B20Ch
90h
USCI_A/B204h
90h
USCI_A/B204h
90h
USCI_A/B204h
90h
ADC12_A208h
D1h
InterruptsTB0.CCIFG0164h
TB0.CCIFG1..6165h
WDTIFG140h
USCI_A0190h
USCI_B0191h
ADC12_A1D0h
TA0.CCIFG0160h
TA0.CCIFG1..4161h
USCI_A2194h
USCI_B2195h
DMA146h
TA1.CCIFG0162h
TA1.CCIFG1..2163h
P1150h
USCI_A1192h
USCI_B1193h
USCI_A3196h
USCI_B3197h
P2151h
RTC_A168h
Delimiter100h