JAJSJ40M June 2007 – March 2022 MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619
PRODUCTION DATA
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 supports multiple capture/compares, PWM outputs, and interval timing (see Table 9-12). Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
INPUT PIN NUMBER | DEVICE INPUT SIGNAL | MODULE INPUT NAME | MODULE BLOCK | MODULE OUTPUT SIGNAL | OUTPUT PIN NUMBER | ||
---|---|---|---|---|---|---|---|
ZCA, ZQW | PM, PN | PM, PN | ZCA, ZQW | ||||
G2 - P1.0 | 12 - P1.0 | TACLK | TACLK | Timer | NA | ||
ACLK | ACLK | ||||||
SMCLK | SMCLK | ||||||
M2 - P2.1 | 21 - P2.1 | TAINCLK | INCLK | ||||
H1 - P1.1 | 13 - P1.1 | TA0 | CCI0A | CCR0 | TA0 | 13 - P1.1 | H1 - P1.1 |
M3 - P2.2 | 22 - P2.2 | TA0 | CCI0B | 17 - P1.5 | K1 - P1.5 | ||
DVSS | GND | 27 - P2.7 | L5 - P2.7 | ||||
DVCC | VCC | ||||||
H2 - P1.2 | 14 - P1.2 | TA1 | CCI1A | CCR1 | TA1 | 14 - P1.2 | H2 - P1.2 |
CAOUT (internal) | CCI1B | 18 - P1.6 | K2 - P1.6 | ||||
DVSS | GND | 23 - P2.3 | L3 - P2.3 | ||||
DVCC | VCC | ADC12 (internal) | |||||
DAC12_0 (internal) | |||||||
DAC12_1 (internal) | |||||||
J1 - P1.3 | 15 - P1.3 | TA2 | CCI2A | CCR2 | TA2 | 15 - P1.3 | J1 - P1.3 |
ACLK (internal) | CCI2B | 19 - P1.7 | L1 - P1.7 | ||||
DVSS | GND | 24 - P2.4 | L4 - P2.4 | ||||
DVCC | VCC |