Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.
Legend | |
rw | Bit can be read and written. |
rw-0, rw-1 | Bit can be read and written. It is Reset or Set by PUC. |
rw-(0), rw-(1) | Bit can be read and written. It is Reset or Set by POR. |
| | SFR bit is not present in device. |
Figure 9-2 Interrupt Enable Register 1 (Address = 00h) Table 9-4 Interrupt Enable Register 1 DescriptionBIT | FIELD | TYPE | RESET | DESCRIPTION |
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5 | ACCVIE | RW | 0h | Flash access violation interrupt enable |
4 | NMIIE | RW | 0h | (Non)maskable interrupt enable |
1 | OFIE | RW | 0h | Oscillator fault interrupt enable |
0 | WDTIE | RW | 0h | Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if the watchdog timer is configured in interval timer mode. |
Figure 9-3 Interrupt Enable Register 2 (Address = 01h) Table 9-5 Interrupt Enable Register 2 DescriptionBIT | FIELD | TYPE | RESET | DESCRIPTION |
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3 | UCB0TXIE | RW | 0h | USCI_B0 transmit interrupt enable |
2 | UCB0RXIE | RW | 0h | USCI_B0 receive interrupt enable |
1 | UCA0TXIE | RW | 0h | USCI_A0 transmit interrupt enable |
0 | UCA0RXIE | RW | 0h | USCI_A0 receive interrupt enable |
Figure 9-4 Interrupt Flag Register 1 (Address = 02h) Table 9-6 Interrupt Flag Register 1 DescriptionBIT | FIELD | TYPE | RESET | DESCRIPTION |
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4 | NMIIFG | RW | 0h | Set by the
RST/NMI pin |
3 | RSTIFG | RW | 0h | External reset interrupt flag. Set on a reset condition at
RST/NMI pin in reset mode. Reset on VCC power up. |
2 | PORIFG | RW | 1h | Power-on reset interrupt flag. Set on VCC power up. |
1 | OFIFG | RW | 1h | Flag set on oscillator fault. |
0 | WDTIFG | RW | 0h | Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power on or a reset condition at the
RST/NMI pin in reset mode. |
Figure 9-5 Interrupt Flag Register 2 (Address = 03h) Table 9-7 Interrupt Flag Register 2 DescriptionBIT | FIELD | TYPE | RESET | DESCRIPTION |
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3 | UCB0TXIFG | RW | 0h | USCI_B0 transmit interrupt flag |
2 | UCB0RXIFG | RW | 1h | USCI_B0 receive interrupt flag |
1 | UCA0TXIFG | RW | 1h | USCI_A0 transmit interrupt flag |
0 | UCA0RXIFG | RW | 0h | USCI_A0 receive interrupt flag |