JAJSFS9R August   2010  – September 2018 MSP430F5131 , MSP430F5132 , MSP430F5151 , MSP430F5152 , MSP430F5171 , MSP430F5172

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.5, P3.2 to P3.7, and PJ.0 to PJ.6)
    8. 5.8  Schmitt-Trigger Inputs – General-Purpose I/O (P1.6 and P1.7, P2.0 to P2.7, and P3.0 and P3.1)
    9. 5.9  Inputs – Ports P1 and P2
    10. 5.10 Leakage Current – General-Purpose I/O
    11. 5.11 Outputs – Ports P1, P3, PJ (Full Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6)
    12. 5.12 Outputs – Ports P1 to P3 (Full Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
    13. 5.13 Outputs – Ports P1, P3, PJ (Reduced Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6)
    14. 5.14 Outputs – Ports P1 to P3 (Reduced Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
    15. 5.15 Output Frequency – Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    16. 5.16 Output Frequency – Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    17. 5.17 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    18. 5.18 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    19. 5.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    20. 5.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    21. 5.21 Crystal Oscillator, XT1, Low-Frequency Mode
    22. 5.22 Crystal Oscillator, XT1, High-Frequency Mode
    23. 5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 5.24 Internal Reference, Low-Frequency Oscillator (REFO)
    25. 5.25 DCO Frequency
    26. 5.26 PMM, Brownout Reset (BOR)
    27. 5.27 PMM, Core Voltage
    28. 5.28 PMM, SVS High Side
    29. 5.29 PMM, SVM High Side
    30. 5.30 PMM, SVS Low Side
    31. 5.31 PMM, SVM Low Side
    32. 5.32 Wake-up Times From Low-Power Modes
    33. 5.33 Timer_A
    34. 5.34 USCI (UART Mode)
    35. 5.35 USCI (SPI Master Mode)
    36. 5.36 USCI (SPI Slave Mode)
    37. 5.37 USCI (I2C Mode)
    38. 5.38 10-Bit ADC, Power Supply and Input Range Conditions (MSP430F51x2 Devices Only)
    39. 5.39 10-Bit ADC, Timing Parameters (MSP430F51x2 Devices Only)
    40. 5.40 10-Bit ADC, Linearity Parameters (MSP430F51x2 Devices Only)
    41. 5.41 REF, External Reference (MSP430F51x2 Devices Only)
    42. 5.42 REF, Built-In Reference (MSP430F51x2 Devices Only)
    43. 5.43 Comparator_B
    44. 5.44 Timer_D, Power Supply and Reference Clock
    45. 5.45 Timer_D, Local Clock Generator Frequency
    46. 5.46 Timer_D, Trimmed Clock Frequencies
    47. 5.47 Timer_D, Frequency Multiplication Mode
    48. 5.48 Timer_D, Input Capture and Output Compare Timing
    49. 5.49 Flash Memory
    50. 5.50 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  Flash Memory
    8. 6.8  RAM
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
      2. 6.9.2  Port Mapping Controller
      3. 6.9.3  Oscillator and System Clock
      4. 6.9.4  Power-Management Module (PMM)
      5. 6.9.5  Hardware Multiplier
      6. 6.9.6  Watchdog Timer (WDT_A)
      7. 6.9.7  System Module (SYS)
      8. 6.9.8  DMA Controller
      9. 6.9.9  Universal Serial Communication Interface (USCI)
      10. 6.9.10 TA0
      11. 6.9.11 TD0
      12. 6.9.12 TD1
      13. 6.9.13 Comparator_B
      14. 6.9.14 ADC10_A (MSP430F51x2 Only)
      15. 6.9.15 CRC16
      16. 6.9.16 Reference (REF) Module Voltage Reference
      17. 6.9.17 Embedded Emulation Module (EEM) (S Version)
      18. 6.9.18 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.5) Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1 (P1.6 to P1.7) Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      4. 6.10.4  Port P3 (P3.0 and P3.1) Input/Output With Schmitt Trigger
      5. 6.10.5  Port P3 (P3.2 and P3.3) Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3 (P3.4) Input/Output With Schmitt Trigger
      7. 6.10.7  Port P3 (P3.5) Input/Output With Schmitt Trigger
      8. 6.10.8  Port P3 (P3.6) Input/Output With Schmitt Trigger
      9. 6.10.9  Port P3 (P3.7) Input/Output With Schmitt Trigger
      10. 6.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      11. 6.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
      12. 6.10.12 Port J (PJ.4) Input/Output With Schmitt Trigger
      13. 6.10.13 Port J (PJ.5) Input/Output With Schmitt Trigger
      14. 6.10.14 Port J (PJ.6) Input/Output With Schmitt Trigger
    11. 6.11 Device Descriptors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1  使い始めと次の手順
    2. 7.2  Device Nomenclature
    3. 7.3  ツールとソフトウェア
    4. 7.4  ドキュメントのサポート
    5. 7.5  関連リンク
    6. 7.6  Community Resources
    7. 7.7  商標
    8. 7.8  静電気放電に関する注意事項
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9.2 Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to Port P1, Port P2, and Port P3 (see Table 6-6).

Table 6-6 Port Mapping Mnemonics and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
1 PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI)
2 PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI – output)
PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)
3 PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)
4 PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI – input)
PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)
5 PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)
6 PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI)
7 PM_TD0.0 TD0 input capture channel 0 TD0 output compare channel 0
8 PM_TD0.1 TD0 input capture channel 1 TD0 output compare channel 1
9 PM_TD0.2 TD0 input capture channel 2 TD0 output compare channel 2
10 PM_TD1.0 TD1 input capture channel 0 TD1 output compare channel 0
11 PM_TD1.1 TD1 input capture channel 1 TD1 output compare channel 1
12 PM_TD1.2 TD1 input capture channel 2 TD1 output compare channel 2
13 PM_CLR1TD0.0 TD0 external clear input TD0 output compare channel 0
PM_FLT1_2TD0.0 TD0 fault input channel 2
14 PM_FLT1_0TD0.1 TD0 fault input channel 0 TD0 output compare channel 1
15 PM_FLT1_1TD0.2 TD0 fault input channel 1 TD0 output compare channel 2
16 PM_CLR2TD1.0 TD1 external clear input (controlled by module input enable) TD1 output compare channel 0
PM_FLT2_1TD1.0 TD1 fault input channel 1 (controlled by module input enable)
17 PM_FLT2_2TD1.1 TD1 fault input channel 2 TD1 output compare channel 1
18 PM_FLT2_0TD1.2 TD1 fault input channel 0 TD1 output compare channel 2
19 PM_TD0.0SMCLK TD0 input capture channel 0 SMCLK output
20 PM_TA0CLKCBOUT TA0 input clock Comparator_B output
21 PM_TD0CLKMCLK TD0 input clock MCLK output
22 PM_TA0_0 TA0 input capture channel 0 TA0 output compare channel 0
23 PM_TA0_1 TA0 input capture channel 1 TA0 output compare channel 1
24 PM_TA0_2 TA0 input capture channel 2 TA0 output compare channel 2
25 PM_DMAE0SMCLK DMAE0 input SMCLK output
26 PM_DMAE1MCLK DMAE1 input MCLK output
27 PM_DMAE2SVM DMAE2 input SVM output
28 PM_TD0OUTH TD0 3-state input ADC10CLK
29 PM_TD1OUTH TD1 3-state input ACLK
30 Reserved None DVSS
31 (0FFh)(1) PM_ANALOG Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are ignored, which results in a read out value of 31.

Table 6-7 lists the default assignments for all pins that support port mapping.

Table 6-7 Default Mapping

PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
P1.0/PM_UCA0CLK/
PM_UCB0STE/A0/CB0		 PM_UCA0CLK
PM_UCB0STE		 USCI_A0 clock input/output (direction controlled by USCI) USCI_B0 SPI slave transmit enable (direction controlled by USCI)
P1.1/PM_UCA0TXD/
PM_UCA0SIMO/A1/CB1		 PM_UCA0TXD
PM_UCA0SIMO		 USCI_A0 UART TXD (Direction controlled by USCI – output) USCI_A0 SPI slave in master out (direction controlled by USCI)
P1.2/PM_UCA0RXD/
PM_UCA0SOMI/A2/CB2		 PM_UCA0RXD
PM_UCA0SOMI		 USCI_A0 UART RXD (Direction controlled by USCI – input) USCI_A0 SPI slave out master in (direction controlled by USCI)
P1.3/PM_UCB0CLK/
PM_UCA0STE/A3/CB3		 PM_UCB0CLK
PM_UCA0STE		 USCI_B0 clock input/output (direction controlled by USCI) USCI_A0 SPI slave transmit enable (direction controlled by USCI)
P1.4/PM_UCB0SIMO/
PM_UCB0SDA/A4/CB4		 PM_UCB0SIMO
PM_UCB0SDA		 USCI_B0 SPI slave in master out (direction controlled by USCI) USCI_B0 I2C data (open drain and direction controlled by USCI)
P1.5/PM_UCB0SOMI/
PM_UCB0SCL/A5/CB5		 PM_UCB0SOMI
PM_UCB0SCL		 USCI_B0 SPI slave out master in (direction controlled by USCI) USCI_B0 I2C clock (open drain and direction controlled by USCI)
P1.6/PM_TD0.0 PM_TD0.0 TD0 input capture channel 0 TD0 output compare channel 0
P1.7/PM_TD0.1 PM_TD0.1 TD0 input capture channel 1 TD0 output compare channel 1
P2.0/PM_TD0.2 PM_TD0.2 TD0 input capture channel 2 TD0 output compare channel 2
P2.1/PM_TD1.0 PM_TD1.0 TD1 input capture channel 0 TD1 output compare channel 0
P2.2/PM_TD1.1 PM_TD1.1 TD1 input capture channel 1 TD1 output compare channel 1
P2.3/PM_TD1.2 PM_TD1.2 TD1 input capture channel 2 TD1 output compare channel 2
P2.4/PM_TEC0CLR/
PM_TEC0FLT2/PM_TD0.0		 PM_CLR1TD0.0
PM_FLT1_2TD0.0		 TD0 external clear input (controlled by module input enable)
TD0 fault input channel 2 (controlled by module input enable)		 TD0 output compare channel 0
P2.5/PM_TEC0FLT0/PM_TD0.1 PM_FLT1_0TD0.1 TD0 fault input channel 0 TD0 output compare channel 1
P2.6/PM_TEC0FLT1/PM_TD0.2 PM_FLT1_1TD0.2 TD0 fault input channel 1 TD0 output compare channel 2
P2.7/PM_TEC1CLR/
PM_TEC1FLT1/PM_TD1.0		 PM_CLR2TD1.0
PM_FLT2_1TD1.0		 TD1 external clear input (controlled by module input enable)
TD1 fault input channel 1 (controlled by module input enable)		 TD1 output compare channel 0
P3.0/PM_TEC1FLT2/
PM_TD1.1		 PM_FLT2_2TD1.1 TD1 fault input channel 2 TD1 output compare channel 1
P3.1/PM_TEC1FLT0/
PM_TD1.2		 PM_FLT2_0TD1.2 TD1 fault input channel 0 TD1 output compare channel 2
P3.2/PM_TD0.0/
PM_SMCLK/CB14		 PM_TD0.0SMCLK TD0 input capture channel 0 SMCLK output
P3.3/PM_TA0CLK/
PM_CBOUT/CB13		 PM_TA0CLKCBOUT TA0 input clock Comparator_B output
P3.4/PM_TD0CLK/
PM_MCLK		 PM_TD0CLKMCLK TD0 input clock MCLK output
P3.5/PM_TA0.2/
VEREF+/CB12 		PM_TA3_2 TA0 input capture channel 0 TA0 output compare channel 0
P3.6/PM_TA0.1/A7
VEREF-/CB11 		PM_TA3_1 TA0 input capture channel 1 TA0 output compare channel 1
P3.7/PM_TA0.0/
A6/CB10		 PM_TA3_0 TA0 input capture channel 2 TA0 output compare channel 2