JAJSFS9R August 2010 – September 2018 MSP430F5131 , MSP430F5132 , MSP430F5151 , MSP430F5152 , MSP430F5171 , MSP430F5172
PRODUCTION DATA.
Table 4-1 describes the signals for all device and package variants.
TERMINAL | I/O(1) | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | NO.(3) | ||||
RSB | DA | YFF | |||
P1.0/
PM_UCA0CLK/ <br/> PM_UCB0STE/ A0(4)/ CB0 |
1 | 5 | B5 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function(2)
Default mapping: Clock signal input – USCI_A0 SPI slave mode; Clock signal output – USCI_A0 SPI master mode Default mapping: Slave transmit enable – USCI_B0 SPI mode Analog input A0 – 10-bit ADC(4) Comparator_B Input 0 |
P1.1/
PM_UCA0TXD/ PM_UCA0SIMO/ A1(4)/ CB1 |
2 | 6 | B6 | I/O | General-purpose digital I/O
Default mapping: Transmit data – USCI_A0 UART mode Default mapping: Slave in, master out – USCI_A0 SPI mode Analog input A1 – 10-bit ADC(4) Comparator_B Input 1 |
P1.2/
PM_UCA0RXD/ PM_UCA0SOMI/ A2(4)/ CB2 |
3 | 7 | C5 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Receive data – USCI_A0 UART mode Default mapping: Slave out, master in – USCI_A0 SPI mode Analog input A2 – 10-bit ADC(4) Comparator_B Input 2 |
P1.3/
PM_UCB0CLK/ <br/> PM_UCA0STE/ A3(4)/ CB3 |
4 | 8 | C6 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Clock signal input – USCI_B0 SPI slave mode; Clock signal output – USCI_B0 SPI master mode Default mapping: Slave transmit enable – USCI_A0 SPI mode Analog input A3 – 10-bit ADC(4) Comparator_B Input 3 |
P1.4/
PM_UCB0SIMO/ PM_UCB0SDA/ A4(4)/ CB4 |
5 | 9 | D5 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave in, master out – USCI_B0 SPI mode Default mapping: I2C data – USCI_B0 I2C mode Analog input A4 – 10-bit ADC(4) Comparator_B Input 4 |
P1.5/
PM_UCB0SOMI/ PM_UCB0SCL/ A5(4)/ CB5 |
6 | 10 | D6 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave out, master in – USCI_B0 SPI mode Default mapping: I2C clock – USCI_B0 I2C mode Analog input A5 – 10-bit ADC(4) Comparator_B Input 5 |
PJ.0/
SMCLK/ TDO/ CB6 |
7 | 11 | E6 | I/O | General-purpose digital I/O
SMCLK clock output Test data output port Comparator_B Input 6 |
PJ.1/
MCLK/ TDI/TCLK/ CB7 |
8 | 12 | E5 | I/O | General-purpose digital I/O
MCLK clock output Test data input or test clock input Comparator_B Input 7 |
PJ.2/
ADC10CLK/ TMS/ CB8 |
9 | 13 | F6 | I/O | General-purpose digital I/O
ADC10_A clock output Test mode select Comparator_B Input 8 |
PJ.3/
ACLK/ TCK/ CB9 |
10 | 14 | E4 | I/O | General-purpose digital I/O
ACLK output port Test clock Comparator_B Input 9 |
P1.6/
PM_TD0.0 |
11 | 15 | G6 | I/O, DVIO | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 CCR0 compare output/capture input |
P1.7/
PM_TD0.1 |
12 | 16 | F5 | I/O, DVIO | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 CCR1 compare output/capture input |
P2.0/
PM_TD0.2 |
13 | 17 | F4 | I/O, DVIO | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 CCR2 compare output/capture input |
P2.1/
PM_TD1.0 |
14 | 18 | G5 | I/O, DVIO | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 CCR0 compare output/capture input |
P2.2/
PM_TD1.1 |
15 | 19 | G4 | I/O, DVIO | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 CCR1 compare output/capture input |
P2.3/
PM_TD1.2 |
16 | 20 | E3 | I/O, DVIO | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 CCR2 compare output/capture input |
DVIO | 17 | 21 | G3 | 5-V tolerant digital I/O power supply | |
DVSS | 18 | 22 | G2 | Digital ground supply | |
P2.4/
PM_TEC0CLR/ PM_TEC0FLT2/ PM_TD0.0 |
19 | 23 | F3 | I/O, DVIO | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 external clear input Default mapping: TD0 fault input channel 2 (controlled by module input enable) Default mapping: TD0 CCR0 compare output |
P2.5/
PM_TEC0FLT0/ PM_TD0.1 |
20 | 24 | G1 | I/O, DVIO | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 fault input channel 0 Default mapping: TD0 CCR1 compare output |
P2.6/
PM_TEC0FLT1/ PM_TD0.2 |
21 | 25 | F2 | I/O, DVIO | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 fault input channel 1 Default mapping: TD0 CCR2 compare output |
P2.7/
PM_TEC1CLR/ PM_TEC1FLT1/ PM_TD1.0 |
22 | 26 | E2 | I/O, DVIO | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 external clear Default mapping: TD1 fault input channel 1 (controlled by module input enable) Default mapping: TD1 CCR0 compare output |
P3.0/
PM_TEC1FLT2/ PM_TD1.1 |
23 | 27 | F1 | I/O, DVIO | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 fault input channel 2 Default mapping: TD1 CCR1 compare output |
P3.1/
PM_TEC1FLT0/ PM_TD1.2 |
24 | 28 | E1 | I/O, DVIO | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD1 fault input channel 0 Default mapping: TD1 CCR2 compare output |
VCORE | 25 | 29 | D1 | Regulated core power supply | |
DVSS | 26 | 30 | C1 | Digital ground supply | |
DVCC | 27 | 31 | B1 | Digital power supply | |
PJ.6/
TD1CLK/ TD0.1/ CB15 |
28 | 32 | C2 | I/O | General-purpose digital I/O
TD1 clock input TD0 CCR1 compare output Comparator_B Input 15 |
P3.2/
PM_TD0.0/ PM_SMCLK/ CB14 |
29 | 33 | B2 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 CCR0 capture input Default mapping: SMCLK output Comparator_B Input 14 |
P3.3/
PM_TA0CLK/ PM_CBOUT/ CB13 |
30 | 34 | A1 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TA0 clock input Default mapping: Comparator_B output Comparator_B Input 13 |
P3.4/
PM_TD0CLK/ PM_MCLK |
31 | – | A2 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TD0 clock input Default mapping: MCLK output |
TEST/
SBWTCK |
32 | 35 | D2 | Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock |
|
RST/
NMI/ SBWTDIO |
33 | 36 | B3 | Reset input active low(5)
Nonmaskable interrupt input Spy-Bi-Wire data input/output |
|
P3.5/
PM_TA0.2/ A8(4) VEREF+/ CB12 |
34 | 37 | A3 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TA0 CCR2 compare output/capture input Analog input A8 – 10-bit ADC(4) Positive terminal for the ADC reference voltage for an external applied reference voltage Comparator_B Input 12 |
P3.6/
PM_TA0.1/ A7(4)/ VEREF-/ CB11 |
35 | 38 | A4 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TA0 CCR1 compare output/capture input Analog input A7 – 10-bit ADC(4) Negative terminal for the ADC reference voltage for an external applied reference voltage Comparator_B Input 11 |
P3.7/
PM_TA0.0/ A6(4)/ CB10 |
36 | – | B4 | I/O | General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: TA0 CCR0 compare output/capture input Analog input A6 – 10-bit ADC(4) Comparator_B Input 10 |
AVCC | 37 | 1 | C3 | Analog power supply | |
PJ.4/
XOUT |
38 | 2 | A5 | I/O | General-purpose digital I/O
Output terminal of crystal oscillator |
PJ.5/
XIN |
39 | 3 | A6 | I/O | General-purpose digital I/O
Input terminal for crystal oscillator |
AVSS | 40 | 4 | C4 | Analog ground supply | |
QFN pad | – | NA | NA | Recommended to connect to DVSS externally |