JAJSG88D May 2013 – October 2020 MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
AVCC | Analog supply voltage | AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V |
1.8 | 3.6 | V | ||
V(Ax) | Analog input voltage range(2) | All ADC10_A pins: P1.0 to P1.5 and P3.6 and P3.7 terminals | 0 | AVCC | V | ||
IADC10_A | Operating supply current into AVCC terminal, REF module and reference buffer off | fADC10CLK = 5.0 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 00 |
2.2 V | 60 | 100 | µA | |
3 V | 75 | 110 | |||||
Operating supply current into AVCC terminal, REF module on, reference buffer on | fADC10CLK = 5.0 MHz, ADC10ON = 1, REFON = 1, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 01 |
3 V | 113 | 150 | µA | ||
Operating supply current into AVCC terminal, REF module off, reference buffer on | fADC10CLK = 5.0 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 10, VEREF = 2.5 V |
3 V | 105 | 140 | µA | ||
Operating supply current into AVCC terminal, REF module off, reference buffer off | fADC10CLK = 5.0 MHz, ADC10ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC10DIV = 0, ADC10SREF = 11, VEREF = 2.5 V |
3 V | 70 | 110 | µA | ||
CI | Input capacitance | Only one terminal Ax can be selected at one time from the pad to the ADC10_A capacitor array including wiring and pad | 2.2 V | 3.5 | pF | ||
RI | Input MUX ON resistance | AVCC > 2 V, 0 V ≤ VAx ≤ AVCC | 36 | kΩ | |||
1.8 V < AVCC < 2 V, 0 V ≤ VAx ≤ AVCC | 96 |