JAJSG88D May 2013 – October 2020 MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259
PRODUCTION DATA
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 supports multiple captures or compares, PWM outputs, and interval timing (see Table 9-12). TA0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
INPUT PIN NUMBER | DEVICE INPUT SIGNAL | MODULE INPUT SIGNAL | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL | OUTPUT PIN NUMBER |
---|---|---|---|---|---|---|
RGC, ZXH, ZQE | RGC, ZXH, ZQE | |||||
18, H2 - P1.0 | TA0CLK | TACLK | Timer | NA | NA | |
ACLK (internal) | ACLK | |||||
SMCLK (internal) | SMCLK | |||||
18, H2 - P1.0 | TA0CLK | TACLK | ||||
19, H3 - P1.1 | TA0.0 | CCI0A | CCR0 | TA0 | TA0.0 | 19, H3 - P1.1 |
DVSS | CCI0B | |||||
DVSS | GND | |||||
DVCC | VCC | |||||
20, J3 - P1.2 | TA0.1 | CCI1A | CCR1 | TA1 | TA0.1 | 20, J3 - P1.2 |
CBOUT (internal) | CCI1B | ADC10 (internal) ADC10SHSx = {1} |
||||
DVSS | GND | |||||
DVCC | VCC | |||||
21, G4 - P1.3 | TA0.2 | CCI2A | CCR2 | TA2 | TA0.2 | 21, G4 - P1.3 |
ACLK (internal) | CCI2B | |||||
DVSS | GND | |||||
DVCC | VCC | |||||
22, H4 - P1.4 | TA0.3 | CCI3A | CCR3 | TA3 | TA0.3 | 22, H4 - P1.4 |
DVSS | CCI3B | |||||
DVSS | GND | |||||
DVCC | VCC | |||||
23, J4 - P1.5 | TA0.4 | CCI4A | CCR4 | TA4 | TA0.4 | 23, J4 - P1.5 |
DVSS | CCI4B | |||||
DVSS | GND | |||||
DVCC | VCC |