JAJSG88 データシート

JAJSG88D May 2013 – October 2020 MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RGC|64
- MPQF125F
ZQE|80
- MPBG269E

サーマルパッド・メカニカル・データ

RGC|64
- QFND102O

発注情報

8.48 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		V_CC	V_IO	MIN	TYP	MAX	UNIT
f_SBW	Spy-Bi-Wire input frequency	2.2 V, 3 V	1.62 V to 1.98 V	0		20	MHz
t_SBW,Low	Spy-Bi-Wire low clock pulse duration	2.2 V, 3 V	1.62 V to 1.98 V	0.025		15	µs
t_{SBW, En}	Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)⁽¹⁾		1.62 V to 1.98 V			1	µs
t_SBW,Rst	Spy-Bi-Wire return to normal operation time	2.2 V, 3 V	1.62 V to 1.98 V	15		100	µs
f_TCK	TCK input frequency for 4-wire JTAG⁽²⁾	2.2 V	1.62 V to 1.98 V	0		5	MHz
f_TCK	TCK input frequency for 4-wire JTAG⁽²⁾	3 V	1.62 V to 1.98 V	0		10	MHz
R_internal	Internal pulldown resistance on TEST	2.2 V, 3 V	1.62 V to 1.98 V	45	60	80	kΩ

(1) Tools that access the Spy-Bi-Wire interface must wait for the t_SBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge.

(2) f_TCK may be restricted to meet the timing requirements of the module selected.