JAJSG88D May 2013 – October 2020 MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259
PRODUCTION DATA
- 1 特長
- 2 アプリケーション
- 3 概要
- 4 Functional Block Diagram
- 5 Revision History
- 6 Device Comparison
- 7 Terminal Configuration and Functions
-
8 Specifications
- 8.1 Absolute Maximum Ratings
- 8.2 ESD Ratings
- 8.3 Recommended Operating Conditions
- 8.4 Active Mode Supply Current Into VCC Excluding External Current
- 8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
- 8.6 Thermal Resistance Characteristics
- 8.7 Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC)
- 8.8 Schmitt-Trigger Inputs – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN)
- 8.9 Inputs – Interrupts DVCC Domain Port P6 (P6.0 to P6.7)
- 8.10 Inputs – Interrupts DVIO Domain Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
- 8.11 Leakage Current – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
- 8.12 Leakage Current – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
- 8.13 Outputs – General-Purpose I/O DVCC Domain (Full Drive Strength) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
- 8.14 Outputs – General-Purpose I/O DVCC Domain (Reduced Drive Strength) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
- 8.15 Outputs – General-Purpose I/O DVIO Domain (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
- 8.16 Outputs – General-Purpose I/O DVIO Domain (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
- 8.17 Output Frequency – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
- 8.18 Output Frequency – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
- 8.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
- 8.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
- 8.21 Crystal Oscillator, XT1, Low-Frequency Mode
- 8.22 Crystal Oscillator, XT2
- 8.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- 8.24 Internal Reference, Low-Frequency Oscillator (REFO)
- 8.25 DCO Frequency
- 8.26 PMM, Brownout Reset (BOR)
- 8.27 PMM, Core Voltage
- 8.28 PMM, SVS High Side
- 8.29 PMM, SVM High Side
- 8.30 PMM, SVS Low Side
- 8.31 PMM, SVM Low Side
- 8.32 Wake-up Times From Low-Power Modes and Reset
- 8.33 Timer_A
- 8.34 Timer_B
- 8.35 USCI (UART Mode) Clock Frequency
- 8.36 USCI (UART Mode)
- 8.37 USCI (SPI Master Mode) Clock Frequency
- 8.38 USCI (SPI Master Mode)
- 8.39 USCI (SPI Slave Mode)
- 8.40 USCI (I2C Mode)
- 8.41 10-Bit ADC, Power Supply and Input Range Conditions
- 8.42 10-Bit ADC, Timing Parameters
- 8.43 10-Bit ADC, Linearity Parameters
- 8.44 REF, External Reference
- 8.45 REF, Built-In Reference
- 8.46 Comparator_B
- 8.47 Flash Memory
- 8.48 JTAG and Spy-Bi-Wire Interface
- 8.49 DVIO BSL Entry
-
9 Detailed Description
- 9.1 CPU
- 9.2 Operating Modes
- 9.3 Interrupt Vector Addresses
- 9.4 Memory Organization
- 9.5 Bootloader (BSL)
- 9.6 JTAG Operation
- 9.7 Flash Memory
- 9.8 RAM
- 9.9
Peripherals
- 9.9.1 Digital I/O
- 9.9.2 Port Mapping Controller
- 9.9.3 Oscillator and System Clock
- 9.9.4 Power-Management Module (PMM)
- 9.9.5 Hardware Multiplier
- 9.9.6 Real-Time Clock (RTC_A)
- 9.9.7 Watchdog Timer (WDT_A)
- 9.9.8 System Module (SYS)
- 9.9.9 DMA Controller
- 9.9.10 Universal Serial Communication Interface (USCI)
- 9.9.11 TA0
- 9.9.12 TA1
- 9.9.13 TA2
- 9.9.14 TB0
- 9.9.15 Comparator_B
- 9.9.16 ADC10_A
- 9.9.17 CRC16
- 9.9.18 Reference (REF) Module Voltage Reference
- 9.9.19 Embedded Emulation Module (EEM) (S Version)
- 9.9.20 Peripheral File Map
- 9.10
Input/Output Diagrams
- 9.10.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
- 9.10.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
- 9.10.3 Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
- 9.10.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
- 9.10.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
- 9.10.6 Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
- 9.10.7 Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
- 9.10.8 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
- 9.10.9 Port P7 (P7.0 to P7.5) Input/Output With Schmitt Trigger
- 9.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
- 9.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
- 9.11 Device Descriptors
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
- RGC|64
発注情報
8.39 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-15 and Figure 8-16)
(see Figure 8-15 and Figure 8-16)
| PARAMETER | TEST CONDITIONS | VCC | VIO | MIN | MAX | UNIT | |
|---|---|---|---|---|---|---|---|
| tSTE,LEAD | STE lead time, STE low to clock | PMMCOREV = 0 | 1.8 V | 1.62 V to 1.80 V | 12 | ns | |
| 3.0 V | 1.62 V to 1.98 V | 12 | |||||
| PMMCOREV = 3 | 2.4 V | 1.62 V to 1.98 V | 10 | ||||
| 3.0 V | 1.62 V to 1.98 V | 10 | |||||
| tSTE,LAG | STE lag time, Last clock to STE high | PMMCOREV = 0 | 1.8 V | 1.62 V to 1.80 V | 6 | ns | |
| 3.0 V | 1.62 V to 1.98 V | 6 | |||||
| PMMCOREV = 3 | 2.4 V | 1.62 V to 1.98 V | 6 | ||||
| 3.0 V | 1.62 V to 1.98 V | 6 | |||||
| tSTE,ACC | STE access time, STE low to SOMI data out | PMMCOREV = 0 | 1.8 V | 1.62 V to 1.80 V | 65 | ns | |
| 3.0 V | 1.62 V to 1.98 V | 65 | |||||
| PMMCOREV = 3 | 2.4 V | 1.62 V to 1.98 V | 45 | ||||
| 3.0 V | 1.62 V to 1.98 V | 45 | |||||
| tSTE,DIS | STE disable time, STE high to SOMI high impedance | PMMCOREV = 0 | 1.8 V | 1.62 V to 1.80 V | 35 | ns | |
| 3.0 V | 1.62 V to 1.98 V | 35 | |||||
| PMMCOREV = 3 | 2.4 V | 1.62 V to 1.98 V | 25 | ||||
| 3.0 V | 1.62 V to 1.98 V | 25 | |||||
| tSU,SI | SIMO input data setup time | PMMCOREV = 0 | 1.8 V | 1.62 V to 1.80 V | 5 | ns | |
| 3.0 V | 1.62 V to 1.98 V | 5 | |||||
| PMMCOREV = 3 | 2.4 V | 1.62 V to 1.98 V | 5 | ||||
| 3.0 V | 1.62 V to 1.98 V | 5 | |||||
| tHD,SI | SIMO input data hold time | PMMCOREV = 0 | 1.8 V | 1.62 V to 1.80 V | 5 | ns | |
| 3.0 V | 1.62 V to 1.98 V | 5 | |||||
| PMMCOREV = 3 | 2.4 V | 1.62 V to 1.98 V | 5 | ||||
| 3.0 V | 1.62 V to 1.98 V | 5 | |||||
| tVALID,SO | SOMI output data valid time(2) | UCLK edge to SOMI valid, CL = 20 pF, PMMCOREV = 0 | 1.8 V | 1.62 V to 1.80 V | 75 | ns | |
| 3.0 V | 1.62 V to 1.98 V | 75 | |||||
| UCLK edge to SOMI valid, CL = 20 pF, PMMCOREV = 3 | 2.4 V | 1.62 V to 1.98 V | 50 | ||||
| 3.0 V | 1.62 V to 1.98 V | 50 | |||||
| tHD,SO | SOMI output data hold time(3) | CL = 20 pF, PMMCOREV = 0 | 1.8 V | 1.62 V to 1.80 V | 10 | ns | |
| 3.0 V | 1.62 V to 1.98 V | 10 | |||||
| CL = 20 pF, PMMCOREV = 3 | 2.4 V | 1.62 V to 1.98 V | 10 | ||||
| 3.0 V | 1.62 V to 1.98 V | 10 | |||||
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 8-15 and Figure 8-16.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 8-15 and Figure 8-16.
Figure 8-15 SPI Slave Mode, CKPH = 0
Figure 8-16 SPI Slave Mode, CKPH = 1