JAJSG72F September   2010  – September 2018 MSP430F5304 , MSP430F5308 , MSP430F5309 , MSP430F5310

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
    8. 5.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
    10. 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    11. 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    12. 5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Crystal Oscillator, XT1, Low-Frequency Mode
    15. 5.15 Crystal Oscillator, XT2
    16. 5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    17. 5.17 Internal Reference, Low-Frequency Oscillator (REFO)
    18. 5.18 DCO Frequency
    19. 5.19 PMM, Brownout Reset (BOR)
    20. 5.20 PMM, Core Voltage
    21. 5.21 PMM, SVS High Side
    22. 5.22 PMM, SVM High Side
    23. 5.23 PMM, SVS Low Side
    24. 5.24 PMM, SVM Low Side
    25. 5.25 Wake-up Times From Low-Power Modes and Reset
    26. 5.26 Timer_A
    27. 5.27 Timer_B
    28. 5.28 USCI (UART Mode) Clock Frequency
    29. 5.29 USCI (UART Mode)
    30. 5.30 USCI (SPI Master Mode) Clock Frequency
    31. 5.31 USCI (SPI Master Mode)
    32. 5.32 USCI (SPI Slave Mode)
    33. 5.33 USCI (I2C Mode)
    34. 5.34 10-Bit ADC, Power Supply and Input Range Conditions
    35. 5.35 10-Bit ADC, Timing Parameters
    36. 5.36 10-Bit ADC, Linearity Parameters
    37. 5.37 REF, External Reference
    38. 5.38 REF, Built-In Reference
    39. 5.39 Comparator_B
    40. 5.40 Ports PU.0 and PU.1
    41. 5.41 LDO-PWR (LDO Power System)
    42. 5.42 Flash Memory
    43. 5.43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU (Link to User's Guide)
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory (Link to User's Guide)
    8. 6.8  RAM (Link to User's Guide)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O (Link to User's Guide)
      2. 6.9.2  Port Mapping Controller (Link to User's Guide)
      3. 6.9.3  Oscillator and System Clock (Link to User's Guide)
      4. 6.9.4  Power-Management Module (PMM) (Link to User's Guide)
      5. 6.9.5  Hardware Multiplier (Link to User's Guide)
      6. 6.9.6  Real-Time Clock (RTC_A) (Link to User's Guide)
      7. 6.9.7  Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.9.8  System Module (SYS) (Link to User's Guide)
      9. 6.9.9  DMA Controller (Link to User's Guide)
      10. 6.9.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.9.11 TA0 (Link to User's Guide)
      12. 6.9.12 TA1 (Link to User's Guide)
      13. 6.9.13 TA2 (Link to User's Guide)
      14. 6.9.14 TB0 (Link to User's Guide)
      15. 6.9.15 Comparator_B (Link to User's Guide)
      16. 6.9.16 ADC10_A (Link to User's Guide)
      17. 6.9.17 CRC16 (Link to User's Guide)
      18. 6.9.18 Reference (REF) Module Voltage Reference (Link to User's Guide)
      19. 6.9.19 LDO and Port U
      20. 6.9.20 Embedded Emulation Module (EEM) (S Version) (Link to User's Guide)
    10. 6.10 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.11.6  Port P5 (P5.2) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P5 (P5.3) Input/Output With Schmitt Trigger
      8. 6.11.8  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      9. 6.11.9  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      10. 6.11.10 Port U (PU.0 and PU.1) Input/Output
      11. 6.11.11 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      12. 6.11.12 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    12. 6.12 Device Descriptors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 使い始めと次の手順
    2. 7.2 Device Nomenclature
    3. 7.3 ツールとソフトウェア
    4. 7.4 ドキュメントのサポート
    5. 7.5 関連リンク
    6. 7.6 Community Resources
    7. 7.7 商標
    8. 7.8 静電気放電に関する注意事項
    9. 7.9 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6-1 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
System Reset
Power up
External reset
Watchdog time-out, password violation
Flash memory password violation		 WDTIFG, KEYV (SYSRSTIV) (1)(3) Reset 0FFFEh 63, highest
System NMI
PMM
Vacant memory access
JTAG mailbox		 SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV) (1) (Non)maskable 0FFFCh 62
User NMI
NMI
Oscillator fault
Flash memory access violation		 NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV) (1)(3) (Non)maskable 0FFFAh 61
Comp_B Comparator B interrupt flags (CBIV) (1)(2) Maskable 0FFF8h 60
TB0 TB0CCR0 CCIFG0 (2) Maskable 0FFF6h 59
TB0 TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV) (1)(2) 		Maskable 0FFF4h 58
Watchdog Timer_A interval timer mode WDTIFG Maskable 0FFF2h 57
USCI_A0 receive or transmit UCA0RXIFG, UCA0TXIFG (UCA0IV) (1)(2) Maskable 0FFF0h 56
USCI_B0 receive or transmit UCB0RXIFG, UCB0TXIFG (UCAB0IV) (1)(2) Maskable 0FFEEh 55
ADC10_A ADC10IFG0 (1)(2)(5) Maskable 0FFECh 54
TA0 TA0CCR0 CCIFG0 (2) Maskable 0FFEAh 53
TA0 TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV) (1)(2) 		Maskable 0FFE8h 52
LDO-PWR LDOOFFIG, LDOONIFG, LDOOVLIFG Maskable 0FFE6h 51
DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) (1)(2) Maskable 0FFE4h 50
TA1 TA1CCR0 CCIFG0 (2) Maskable 0FFE2h 49
TA1 TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV) (1)(2) 		Maskable 0FFE0h 48
I/O port P1 P1IFG.0 to P1IFG.7 (P1IV) (1)(2) Maskable 0FFDEh 47
USCI_A1 receive or transmit UCA1RXIFG, UCA1TXIFG (UCA1IV) (1)(2) Maskable 0FFDCh 46
USCI_B1 receive or transmit UCB1RXIFG, UCB1TXIFG (UCB1IV) (1)(2) Maskable 0FFDAh 45
TA2 TA2CCR0 CCIFG0 (2) Maskable 0FFD8h 44
TA2 TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV) (1)(2) 		Maskable 0FFD6h 43
I/O port P2 P2IFG.0 to P2IFG.7 (P2IV) (1)(2) Maskable 0FFD4h 42
RTC_A RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) (1)(2) Maskable 0FFD2h 41
Reserved Reserved (4) 0FFD0h 40
⋮ ⋮
0FF80h 0, lowest
(1) Multiple source flags
(2) Interrupt flags are in the module.
(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations.
(5) Only on devices with ADC, otherwise reserved.