JAJSG72F September 2010 – September 2018 MSP430F5304 , MSP430F5308 , MSP430F5309 , MSP430F5310
PRODUCTION DATA.
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-13). TB0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
INPUT PIN NUMBER | DEVICE INPUT SIGNAL | MODULE INPUT SIGNAL | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL | OUTPUT PIN NUMBER | ||
---|---|---|---|---|---|---|---|---|
RGC, ZQE(2) | RGZ, PT(2) | RGC, ZQE(2) | RGZ, PT(2) | |||||
TB0CLK | TBCLK | Timer | NA | NA | ||||
ACLK (internal) | ACLK | |||||||
SMCLK (internal) | SMCLK | |||||||
TB0CLK | TBCLK | |||||||
TB0.0 | CCI0A | CCR0 | TB0 | TB0.0 | ADC10 (internal)(1)
ADC10SHSx = {2} |
ADC10 (internal)(1)
ADC10SHSx = {2} |
||
TB0.0 | CCI0B | |||||||
DVSS | GND | |||||||
DVCC | VCC | |||||||
TB0.1 | CCI1A | CCR1 | TB1 | TB0.1 | ADC10 (internal)
ADC10SHSx = {3} |
ADC10 (internal)
ADC10SHSx = {3} |
||
CBOUT (internal) | CCI1B | |||||||
DVSS | GND | |||||||
DVCC | VCC | |||||||
TB0.2 | CCI2A | CCR2 | TB2 | TB0.2 | ||||
TB0.2 | CCI2B | |||||||
DVSS | GND | |||||||
DVCC | VCC | |||||||
TB0.3 | CCI3A | CCR3 | TB3 | TB0.3 | ||||
TB0.3 | CCI3B | |||||||
DVSS | GND | |||||||
DVCC | VCC | |||||||
TB0.4 | CCI4A | CCR4 | TB4 | TB0.4 | ||||
TB0.4 | CCI4B | |||||||
DVSS | GND | |||||||
DVCC | VCC | |||||||
TB0.5 | CCI5A | CCR5 | TB5 | TB0.5 | ||||
TB0.5 | CCI5B | |||||||
DVSS | GND | |||||||
DVCC | VCC | |||||||
TB0.6 | CCI6A | CCR6 | TB6 | TB0.6 | ||||
ACLK (internal) | CCI6B | |||||||
DVSS | GND | |||||||
DVCC | VCC |