JAJSG72F September   2010  – September 2018 MSP430F5304 , MSP430F5308 , MSP430F5309 , MSP430F5310

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
    8. 5.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
    10. 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    11. 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    12. 5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Crystal Oscillator, XT1, Low-Frequency Mode
    15. 5.15 Crystal Oscillator, XT2
    16. 5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    17. 5.17 Internal Reference, Low-Frequency Oscillator (REFO)
    18. 5.18 DCO Frequency
    19. 5.19 PMM, Brownout Reset (BOR)
    20. 5.20 PMM, Core Voltage
    21. 5.21 PMM, SVS High Side
    22. 5.22 PMM, SVM High Side
    23. 5.23 PMM, SVS Low Side
    24. 5.24 PMM, SVM Low Side
    25. 5.25 Wake-up Times From Low-Power Modes and Reset
    26. 5.26 Timer_A
    27. 5.27 Timer_B
    28. 5.28 USCI (UART Mode) Clock Frequency
    29. 5.29 USCI (UART Mode)
    30. 5.30 USCI (SPI Master Mode) Clock Frequency
    31. 5.31 USCI (SPI Master Mode)
    32. 5.32 USCI (SPI Slave Mode)
    33. 5.33 USCI (I2C Mode)
    34. 5.34 10-Bit ADC, Power Supply and Input Range Conditions
    35. 5.35 10-Bit ADC, Timing Parameters
    36. 5.36 10-Bit ADC, Linearity Parameters
    37. 5.37 REF, External Reference
    38. 5.38 REF, Built-In Reference
    39. 5.39 Comparator_B
    40. 5.40 Ports PU.0 and PU.1
    41. 5.41 LDO-PWR (LDO Power System)
    42. 5.42 Flash Memory
    43. 5.43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU (Link to User's Guide)
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory (Link to User's Guide)
    8. 6.8  RAM (Link to User's Guide)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O (Link to User's Guide)
      2. 6.9.2  Port Mapping Controller (Link to User's Guide)
      3. 6.9.3  Oscillator and System Clock (Link to User's Guide)
      4. 6.9.4  Power-Management Module (PMM) (Link to User's Guide)
      5. 6.9.5  Hardware Multiplier (Link to User's Guide)
      6. 6.9.6  Real-Time Clock (RTC_A) (Link to User's Guide)
      7. 6.9.7  Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.9.8  System Module (SYS) (Link to User's Guide)
      9. 6.9.9  DMA Controller (Link to User's Guide)
      10. 6.9.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.9.11 TA0 (Link to User's Guide)
      12. 6.9.12 TA1 (Link to User's Guide)
      13. 6.9.13 TA2 (Link to User's Guide)
      14. 6.9.14 TB0 (Link to User's Guide)
      15. 6.9.15 Comparator_B (Link to User's Guide)
      16. 6.9.16 ADC10_A (Link to User's Guide)
      17. 6.9.17 CRC16 (Link to User's Guide)
      18. 6.9.18 Reference (REF) Module Voltage Reference (Link to User's Guide)
      19. 6.9.19 LDO and Port U
      20. 6.9.20 Embedded Emulation Module (EEM) (S Version) (Link to User's Guide)
    10. 6.10 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.11.6  Port P5 (P5.2) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P5 (P5.3) Input/Output With Schmitt Trigger
      8. 6.11.8  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      9. 6.11.9  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      10. 6.11.10 Port U (PU.0 and PU.1) Input/Output
      11. 6.11.11 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      12. 6.11.12 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    12. 6.12 Device Descriptors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 使い始めと次の手順
    2. 7.2 Device Nomenclature
    3. 7.3 ツールとソフトウェア
    4. 7.4 ドキュメントのサポート
    5. 7.5 関連リンク
    6. 7.6 Community Resources
    7. 7.7 商標
    8. 7.8 静電気放電に関する注意事項
    9. 7.9 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1 Signal Descriptions

TERMINAL I/O(1) DESCRIPTION
NAME NO.
RGC RGZ, PT ZQE
P6.4/CB4/A4 5 N/A C1 I/O General-purpose digital I/O
Comparator_B input CB4 (not available on RGZ or PT package devices)
Analog input A4 for ADC (not available on RGZ or PT package devices)
P6.5/CB5/A5 6 N/A D2 I/O General-purpose digital I/O
Comparator_B input CB5 (not available on RGZ or PT package devices)
Analog input A5 for ADC (not available on RGZ or PT package devices)
P6.6/CB6/A6 7 N/A D1 I/O General-purpose digital I/O
Comparator_B input CB6 (not available on RGZ or PT package devices)
Analog input A6 for ADC (not available on RGZ or PT package devices)
P6.7/CB7/A7 8 N/A D3 I/O General-purpose digital I/O
Comparator_B input CB7 (not available on RGZ or PT package devices)
Analog input A7 for ADC (not available on RGZ or PT package devices)
P5.0/A8/VeREF+ 9 5 E1 I/O General-purpose digital I/O
Analog input A8 for ADC
Input for an external reference voltage to the ADC
P5.1/A9/VeREF- 10 6 E2 I/O General-purpose digital I/O
Analog input A9 for ADC
Negative terminal for an externally provided ADC reference
AVCC1 11 7 F2 Analog power supply
P5.4/XIN 12 8 F1 I/O General-purpose digital I/O
Input terminal for crystal oscillator XT1
P5.5/XOUT 13 9 G1 I/O General-purpose digital I/O
Output terminal of crystal oscillator XT1
AVSS1 14 10 G2 Analog ground supply
DVCC1 15 11 H1 Digital power supply
DVSS1 16 12 J1 Digital ground supply
VCORE(3) 17 13 J2 Regulated core power supply output (internal use only, no external current loading)
P1.0/TA0CLK/ACLK 18 14 H2 I/O General-purpose digital I/O with port interrupt
TA0 clock signal TA0CLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P1.1/TA0.0 19 15 H3 I/O General-purpose digital I/O with port interrupt
TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
P1.2/TA0.1 20 16 J3 I/O General-purpose digital I/O with port interrupt
TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
P1.3/TA0.2 21 17 G4 I/O General-purpose digital I/O with port interrupt
TA0 CCR2 capture: CCI2A input, compare: Out2 output
P1.4/TA0.3 22 18 H4 I/O General-purpose digital I/O with port interrupt
TA0 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4 23 19 J4 I/O General-purpose digital I/O with port interrupt
TA0 CCR4 capture: CCI4A input, compare: Out4 output
P1.6/TA1CLK/CBOUT 24 20 G5 I/O General-purpose digital I/O with port interrupt
TA1 clock signal TA1CLK input
Comparator_B output
P1.7/TA1.0 25 21 H5 I/O General-purpose digital I/O with port interrupt
TA1 CCR0 capture: CCI0A input, compare: Out0 output
P2.0/TA1.1 26 22 J5 I/O General-purpose digital I/O with port interrupt
TA1 CCR1 capture: CCI1A input, compare: Out1 output
P2.1/TA1.2 27 N/A G6 I/O General-purpose digital I/O with port interrupt
TA1 CCR2 capture: CCI2A input, compare: Out2 output
P2.2/TA2CLK/SMCLK 28 N/A J6 I/O General-purpose digital I/O with port interrupt
TA2 clock signal TA2CLK input ; SMCLK output
P2.3/TA2.0 29 N/A H6 I/O General-purpose digital I/O with port interrupt
TA2 CCR0 capture: CCI0A input, compare: Out0 output
P2.4/TA2.1 30 N/A J7 I/O General-purpose digital I/O with port interrupt
TA2 CCR1 capture: CCI1A input, compare: Out1 output
P2.5/TA2.2 31 N/A J8 I/O General-purpose digital I/O with port interrupt
TA2 CCR2 capture: CCI2A input, compare: Out2 output
P2.6/RTCCLK/DMAE0 32 N/A J9 I/O General-purpose digital I/O with port interrupt
RTC clock output for calibration
DMA external trigger input
P2.7/UCB0STE/UCA0CLK 33 N/A H7 I/O General-purpose digital I/O with port interrupt
Slave transmit enable – USCI_B0 SPI mode
Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
P3.0/UCB0SIMO/UCB0SDA 34 N/A H8 I/O General-purpose digital I/O
Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
P3.1/UCB0SOMI/UCB0SCL 35 N/A H9 I/O General-purpose digital I/O
Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
P3.2/UCB0CLK/UCA0STE 36 N/A G8 I/O General-purpose digital I/O
Clock signal input – USCI_B0 SPI slave mode
Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
P3.3/UCA0TXD/UCA0SIMO 37 N/A G9 I/O General-purpose digital I/O
Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
P3.4/UCA0RXD/UCA0SOMI 38 N/A G7 I/O General-purpose digital I/O
Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
P4.0/PM_UCB1STE/ PM_UCA1CLK 41 29 E8 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave transmit enable – USCI_B1 SPI mode
Default mapping: Clock signal input – USCI_A1 SPI slave mode
Default mapping: Clock signal output – USCI_A1 SPI master mode
P4.1/PM_UCB1SIMO/ PM_UCB1SDA 42 30 E7 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave in, master out – USCI_B1 SPI mode
Default mapping: I2C data – USCI_B1 I2C mode
P4.2/PM_UCB1SOMI/ PM_UCB1SCL 43 31 D9 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave out, master in – USCI_B1 SPI mode
Default mapping: I2C clock – USCI_B1 I2C mode
P4.3/PM_UCB1CLK/ PM_UCA1STE 44 32 D8 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Clock signal input – USCI_B1 SPI slave mode
Default mapping: Clock signal output – USCI_B1 SPI master mode
Default mapping: Slave transmit enable – USCI_A1 SPI mode
DVSS2 39 27 F9 Digital ground supply
DVCC2 40 28 E9 Digital power supply
P4.4/PM_UCA1TXD/ PM_UCA1SIMO 45 33 D7 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Transmit data – USCI_A1 UART mode
Default mapping: Slave in, master out – USCI_A1 SPI mode
P4.5/PM_UCA1RXD/ PM_UCA1SOMI 46 34 C9 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Receive data – USCI_A1 UART mode
Default mapping: Slave out, master in – USCI_A1 SPI mode
P4.6/PM_NONE 47 35 C8 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: no secondary function.
P4.7/PM_NONE 48 36 C7 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: no secondary function.
VSSU 49 37 B8, B9 PU ground supply
PU.0 50 38 A9 I/O General-purpose digital I/O - controlled by PU control register.
Port U is supplied by the LDOO rail.
NC 51 39 B7 I/O No connect.
PU.1 52 40 A8 I/O General-purpose digital I/O - controlled by PU control register
Port U is supplied by the LDOO rail.
LDOI 53 41 A7 LDO input
LDOO 54 42 A6 LDO output
NC 55 43 B6 No connect.
AVSS2 56 44 A5 Analog ground supply
P5.2/XT2IN 57 45 B5 I/O General-purpose digital I/O
Input terminal for crystal oscillator XT2
P5.3/XT2OUT 58 46 B4 I/O General-purpose digital I/O
Output terminal of crystal oscillator XT2
TEST/SBWTCK 59 47 A4 I Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
PJ.0/TDO 60 23 C5 I/O General-purpose digital I/O
Test data output port
PJ.1/TDI/TCLK 61 24 C4 I/O General-purpose digital I/O
Test data input or test clock input
PJ.2/TMS 62 25 A3 I/O General-purpose digital I/O
Test mode select
PJ.3/TCK 63 26 B3 I/O General-purpose digital I/O
Test clock
RST/NMI/SBWTDIO 64 48 A2 I/O Reset input active low(4)
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
P6.0/CB0/A0 1 1 A1 I/O General-purpose digital I/O
Comparator_B input CB0 (not available on F5304 device)
Analog input A0 for ADC
P6.1/CB1/A1 2 2 B2 I/O General-purpose digital I/O
Comparator_B input CB1 (not available on F5304 device)
Analog input A1 for ADC
P6.2/CB2/A2 3 3 B1 I/O General-purpose digital I/O
Comparator_B input CB2 (not available on F5304 device)
Analog input A2 for ADC
P6.3/CB3/A3 4 4 C2 I/O General-purpose digital I/O
Comparator_B input CB3 (not available on F5304 device)
Analog input A3 for ADC
Reserved N/A N/A   (2)
Thermal Pad Pad Pad N/A Exposed thermal pad on QFN packages. TI recommends connection to VSS (not available on PT package devices).
(1) I = input, O = output, N/A = not available
(2) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
(3) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE.
(4) When this pin is configured as reset, the internal pullup resistor is enabled by default.