JAJSG73 データシート

JAJSG73F August 2010 – September 2019 MSP430F5324 , MSP430F5325 , MSP430F5326 , MSP430F5327 , MSP430F5328 , MSP430F5329

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PN|80
- MTQF010B

サーマルパッド・メカニカル・データ

発注情報

5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS⁽¹⁾		V_CC	MIN	TYP	MAX	UNIT
E_I	Integral linearity error⁽²⁾	ADC12SR = 0, REFOUT = 1	f_ADC12CLK ≤ 4.0 MHz	2.2 V, 3 V			±1.7	LSB
E_I	Integral linearity error⁽²⁾	ADC12SR = 0, REFOUT = 0	f_ADC12CLK ≤ 2.7 MHz	2.2 V, 3 V			±2.5	LSB
E_D	Differential linearity error⁽²⁾	ADC12SR = 0, REFOUT = 1	f_ADC12CLK ≤ 4.0 MHz	2.2 V, 3 V	–1.0		+2.0	LSB
		ADC12SR = 0, REFOUT = 1	f_ADC12CLK ≤ 2.7 MHz		–1.0		+1.5
		ADC12SR = 0, REFOUT = 0	f_ADC12CLK ≤ 2.7 MHz		–1.0		+2.5
E_O	Offset error⁽³⁾	ADC12SR = 0, REFOUT = 1	f_ADC12CLK ≤ 4.0 MHz	2.2 V, 3 V		±1.0	±2.0	LSB
E_O	Offset error⁽³⁾	ADC12SR = 0, REFOUT = 0	f_ADC12CLK ≤ 2.7 MHz	2.2 V, 3 V		±1.0	±2.0	LSB
E_G	Gain error⁽³⁾	ADC12SR = 0, REFOUT = 1	f_ADC12CLK ≤ 4.0 MHz	2.2 V, 3 V		±1.0	±2.0	LSB
E_G	Gain error⁽³⁾	ADC12SR = 0, REFOUT = 0	f_ADC12CLK ≤ 2.7 MHz	2.2 V, 3 V			±1.5%⁽⁴⁾	VREF
E_T	Total unadjusted error	ADC12SR = 0, REFOUT = 1	f_ADC12CLK ≤ 4.0 MHz	2.2 V, 3 V		±1.4	±3.5	LSB
E_T	Total unadjusted error	ADC12SR = 0, REFOUT = 0	f_ADC12CLK ≤ 2.7 MHz	2.2 V, 3 V			±1.5%⁽⁴⁾	VREF

(1) The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = V_R+ – V_R–.

(2) Parameters are derived using the histogram method.

(3) Parameters are derived using a best fit curve.

(4) The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this mode the reference voltage used by the ADC12_A is not available on a pin.