JAJSG78F July   2011  – September 2018 MSP430F5340 , MSP430F5341 , MSP430F5342

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics, VQFN (RGZ) Package
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
    8. 5.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
    10. 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
    11. 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
    12. 5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, XT2
    17. 5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 5.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 5.19 DCO Frequency
    20. 5.20 PMM, Brownout Reset (BOR)
    21. 5.21 PMM, Core Voltage
    22. 5.22 PMM, SVS High Side
    23. 5.23 PMM, SVM High Side
    24. 5.24 PMM, SVS Low Side
    25. 5.25 PMM, SVM Low Side
    26. 5.26 Wake-up Times From Low-Power Modes and Reset
    27. 5.27 Timer_A
    28. 5.28 Timer_B
    29. 5.29 USCI (UART Mode) Clock Frequency
    30. 5.30 USCI (UART Mode)
    31. 5.31 USCI (SPI Master Mode) Clock Frequency
    32. 5.32 USCI (SPI Master Mode)
    33. 5.33 USCI (SPI Slave Mode)
    34. 5.34 USCI (I2C Mode)
    35. 5.35 12-Bit ADC, Power Supply and Input Range Conditions
    36. 5.36 12-Bit ADC, Timing Parameters
    37. 5.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    38. 5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 5.40 REF, External Reference
    41. 5.41 REF, Built-In Reference
    42. 5.42 Comparator_B
    43. 5.43 Flash Memory
    44. 5.44 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory
    8. 6.8  RAM
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
      2. 6.9.2  Port Mapping Controller
      3. 6.9.3  Oscillator and System Clock
      4. 6.9.4  Power Management Module (PMM)
      5. 6.9.5  Hardware Multiplier
      6. 6.9.6  Real-Time Clock (RTC_A)
      7. 6.9.7  Watchdog Timer (WDT_A)
      8. 6.9.8  System Module (SYS)
      9. 6.9.9  DMA Controller
      10. 6.9.10 Universal Serial Communication Interface (USCI)
      11. 6.9.11 TA0
      12. 6.9.12 TA1
      13. 6.9.13 TA2
      14. 6.9.14 TB0
      15. 6.9.15 Comparator_B
      16. 6.9.16 ADC12_A
      17. 6.9.17 CRC16
      18. 6.9.18 Reference (REF) Module Voltage Reference
      19. 6.9.19 Embedded Emulation Module (EEM)
      20. 6.9.20 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2 (P2.7) Input/Output With Schmitt Trigger
      3. 6.10.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 6.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5 (P5.2) Input/Output With Schmitt Trigger
      7. 6.10.7  Port P5 (P5.3) Input/Output With Schmitt Trigger
      8. 6.10.8  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      9. 6.10.9  Port P5 (P5.7) Input/Output With Schmitt Trigger
      10. 6.10.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
      11. 6.10.11 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      12. 6.10.12 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11 Device Descriptors
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1  はじめに
    2. 7.2  Device Nomenclature
    3. 7.3  ツールとソフトウェア
    4. 7.4  ドキュメントのサポート
    5. 7.5  関連リンク
    6. 7.6  Community Resources
    7. 7.7  商標
    8. 7.8  静電気放電に関する注意事項
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.33 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 5-13 and Figure 5-14)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
tSTE,LEAD STE lead time, STE low to clock PMMCOREV = 0 1.8 V 11 ns
3 V 8
PMMCOREV = 3 2.4 V 7
3 V 6
tSTE,LAG STE lag time, last clock to STE high PMMCOREV = 0 1.8 V 3 ns
3 V 3
PMMCOREV = 3 2.4 V 3
3 V 3
tSTE,ACC STE access time, STE low to SOMI data out PMMCOREV = 0 1.8 V 66 ns
3 V 50
PMMCOREV = 3 2.4 V 36
3 V 30
tSTE,DIS STE disable time, STE high to SOMI high impedance PMMCOREV = 0 1.8 V 30 ns
3 V 23
PMMCOREV = 3 2.4 V 16
3 V 13
tSU,SI SIMO input data setup time PMMCOREV = 0 1.8 V 5 ns
3 V 5
PMMCOREV = 3 2.4 V 2
3 V 2
tHD,SI SIMO input data hold time PMMCOREV = 0 1.8 V 5 ns
3 V 5
PMMCOREV = 3 2.4 V 5
3 V 5
tVALID,SO SOMI output data valid time(2) UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 0		 1.8 V 76 ns
3 V 60
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 3		 2.4 V 44
3 V 40
tHD,SO SOMI output data hold time(3) CL = 20 pF, PMMCOREV = 0 1.8 V 18 ns
3 V 12
CL = 20 pF, PMMCOREV = 3 2.4 V 10
3 V 8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14.
MSP430F5342 MSP430F5341 MSP430F5340 spi_slv_ckph0.gifFigure 5-13 SPI Slave Mode, CKPH = 0
MSP430F5342 MSP430F5341 MSP430F5340 spi_slv_ckph1.gifFigure 5-14 SPI Slave Mode, CKPH = 1