JAJSG78F
July 2011 – September 2018
MSP430F5340
,
MSP430F5341
,
MSP430F5342
PRODUCTION DATA.
1
デバイスの概要
1.1
特長
1.2
アプリケーション
1.3
概要
1.4
機能ブロック図
2
改訂履歴
3
Device Comparison
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Pin Diagram
4.2
Signal Descriptions
Table 4-1
Signal Descriptions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Active Mode Supply Current Into VCC Excluding External Current
5.5
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
5.6
Thermal Resistance Characteristics, VQFN (RGZ) Package
5.7
Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
5.8
Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
5.9
Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3, RST/NMI)
5.10
Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
5.11
Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
5.12
Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P5.7, P6.1 to P6.5, PJ.0 to PJ.3)
5.13
Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
5.14
Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
5.15
Crystal Oscillator, XT1, Low-Frequency Mode
5.16
Crystal Oscillator, XT2
5.17
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
5.18
Internal Reference, Low-Frequency Oscillator (REFO)
5.19
DCO Frequency
5.20
PMM, Brownout Reset (BOR)
5.21
PMM, Core Voltage
5.22
PMM, SVS High Side
5.23
PMM, SVM High Side
5.24
PMM, SVS Low Side
5.25
PMM, SVM Low Side
5.26
Wake-up Times From Low-Power Modes and Reset
5.27
Timer_A
5.28
Timer_B
5.29
USCI (UART Mode) Clock Frequency
5.30
USCI (UART Mode)
5.31
USCI (SPI Master Mode) Clock Frequency
5.32
USCI (SPI Master Mode)
5.33
USCI (SPI Slave Mode)
5.34
USCI (I2C Mode)
5.35
12-Bit ADC, Power Supply and Input Range Conditions
5.36
12-Bit ADC, Timing Parameters
5.37
12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
5.38
12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
5.39
12-Bit ADC, Temperature Sensor and Built-In VMID
5.40
REF, External Reference
5.41
REF, Built-In Reference
5.42
Comparator_B
5.43
Flash Memory
5.44
JTAG and Spy-Bi-Wire Interface
6
Detailed Description
6.1
CPU
6.2
Operating Modes
6.3
Interrupt Vector Addresses
6.4
Memory Organization
6.5
Bootloader (BSL)
6.6
JTAG Operation
6.6.1
JTAG Standard Interface
6.6.2
Spy-Bi-Wire Interface
6.7
Flash Memory
6.8
RAM
6.9
Peripherals
6.9.1
Digital I/O
6.9.2
Port Mapping Controller
6.9.3
Oscillator and System Clock
6.9.4
Power Management Module (PMM)
6.9.5
Hardware Multiplier
6.9.6
Real-Time Clock (RTC_A)
6.9.7
Watchdog Timer (WDT_A)
6.9.8
System Module (SYS)
6.9.9
DMA Controller
6.9.10
Universal Serial Communication Interface (USCI)
6.9.11
TA0
6.9.12
TA1
6.9.13
TA2
6.9.14
TB0
6.9.15
Comparator_B
6.9.16
ADC12_A
6.9.17
CRC16
6.9.18
Reference (REF) Module Voltage Reference
6.9.19
Embedded Emulation Module (EEM)
6.9.20
Peripheral File Map
6.10
Input/Output Diagrams
6.10.1
Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
6.10.2
Port P2 (P2.7) Input/Output With Schmitt Trigger
6.10.3
Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
6.10.4
Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
6.10.5
Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
6.10.6
Port P5 (P5.2) Input/Output With Schmitt Trigger
6.10.7
Port P5 (P5.3) Input/Output With Schmitt Trigger
6.10.8
Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
6.10.9
Port P5 (P5.7) Input/Output With Schmitt Trigger
6.10.10
Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
6.10.11
Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
6.10.12
Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
6.11
Device Descriptors
7
デバイスおよびドキュメントのサポート
7.1
はじめに
7.2
Device Nomenclature
7.3
ツールとソフトウェア
7.4
ドキュメントのサポート
7.5
関連リンク
7.6
Community Resources
7.7
商標
7.8
静電気放電に関する注意事項
7.9
Export Control Notice
7.10
Glossary
8
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RGZ|48
MPQF123F
サーマルパッド・メカニカル・データ
RGZ|48
QFND031W
発注情報
jajsg78f_oa
jajsg78f_pm
6
Detailed Description