JAJSG52N March   2009  – September 2018 MSP430F5513 , MSP430F5514 , MSP430F5515 , MSP430F5517 , MSP430F5519 , MSP430F5521 , MSP430F5522 , MSP430F5524 , MSP430F5525 , MSP430F5526 , MSP430F5527 , MSP430F5528 , MSP430F5529

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Terminal Functions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
    8. 5.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
    10. 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    11. 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    12. 5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, XT2
    17. 5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 5.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 5.19 DCO Frequency
    20. 5.20 PMM, Brownout Reset (BOR)
    21. 5.21 PMM, Core Voltage
    22. 5.22 PMM, SVS High Side
    23. 5.23 PMM, SVM High Side
    24. 5.24 PMM, SVS Low Side
    25. 5.25 PMM, SVM Low Side
    26. 5.26 Wake-up Times From Low-Power Modes and Reset
    27. 5.27 Timer_A
    28. 5.28 Timer_B
    29. 5.29 USCI (UART Mode) Clock Frequency
    30. 5.30 USCI (UART Mode)
    31. 5.31 USCI (SPI Master Mode) Clock Frequency
    32. 5.32 USCI (SPI Master Mode)
    33. 5.33 USCI (SPI Slave Mode)
    34. 5.34 USCI (I2C Mode)
    35. 5.35 12-Bit ADC, Power Supply and Input Range Conditions
    36. 5.36 12-Bit ADC, Timing Parameters
    37. 5.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    38. 5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 5.40 REF, External Reference
    41. 5.41 REF, Built-In Reference
    42. 5.42 Comparator_B
    43. 5.43 Ports PU.0 and PU.1
    44. 5.44 USB Output Ports DP and DM
    45. 5.45 USB Input Ports DP and DM
    46. 5.46 USB-PWR (USB Power System)
    47. 5.47 USB-PLL (USB Phase-Locked Loop)
    48. 5.48 Flash Memory
    49. 5.49 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU (Link to User's Guide)
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
      1. 6.5.1 USB BSL
      2. 6.5.2 UART BSL
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory (Link to User's Guide)
    8. 6.8  RAM (Link to User's Guide)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O (Link to User's Guide)
      2. 6.9.2  Port Mapping Controller (Link to User's Guide)
      3. 6.9.3  Oscillator and System Clock (Link to User's Guide)
      4. 6.9.4  Power-Management Module (PMM) (Link to User's Guide)
      5. 6.9.5  Hardware Multiplier (Link to User's Guide)
      6. 6.9.6  Real-Time Clock (RTC_A) (Link to User's Guide)
      7. 6.9.7  Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.9.8  System Module (SYS) (Link to User's Guide)
      9. 6.9.9  DMA Controller (Link to User's Guide)
      10. 6.9.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.9.11 TA0 (Link to User's Guide)
      12. 6.9.12 TA1 (Link to User's Guide)
      13. 6.9.13 TA2 (Link to User's Guide)
      14. 6.9.14 TB0 (Link to User's Guide)
      15. 6.9.15 Comparator_B (Link to User's Guide)
      16. 6.9.16 ADC12_A (Link to User's Guide)
      17. 6.9.17 CRC16 (Link to User's Guide)
      18. 6.9.18 Voltage Reference (REF) Module (Link to User's Guide)
      19. 6.9.19 Universal Serial Bus (USB) (Link to User's Guide)
      20. 6.9.20 Embedded Emulation Module (EEM) (Link to User's Guide)
      21. 6.9.21 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.10.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 6.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
      7. 6.10.7  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      8. 6.10.8  Port P5 (P5.6 and P5.7) Input/Output With Schmitt Trigger
      9. 6.10.9  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      10. 6.10.10 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      11. 6.10.11 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      12. 6.10.12 Port P8 (P8.0 to P8.2) Input/Output With Schmitt Trigger
      13. 6.10.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports
      14. 6.10.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 6.10.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11 Device Descriptors (TLV)
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1  使い始めと次の手順
    2. 7.2  Device Nomenclature
    3. 7.3  ツールとソフトウェア
    4. 7.4  ドキュメントのサポート
    5. 7.5  関連リンク
    6. 7.6  Community Resources
    7. 7.7  商標
    8. 7.8  静電気放電に関する注意事項
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.39 12-Bit ADC, Temperature Sensor and Built-In VMID(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VSENSOR See (2) ADC12ON = 1, INCH = 0Ah,
TA = 0°C		 2.2 V 680 mV
3 V 680
TCSENSOR ADC12ON = 1, INCH = 0Ah 2.2 V 2.25 mV/°C
3 V 2.25
tSENSOR(sample) Sample time required if channel 10 is selected(3) ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB		 2.2 V 100 µs
3 V 100
VMID AVCC divider at channel 11,
VAVCC factor		 ADC12ON = 1, INCH = 0Bh 0.48 0.5 0.52 VAVCC
AVCC divider at channel 11 ADC12ON = 1, INCH = 0Bh 2.2 V 1.06 1.1 1.14 V
3 V 1.44 1.5 1.56
tVMID(sample) Sample time required if channel 11 is selected(4) ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB		 2.2 V, 3 V 1000 ns
(1) The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of the temperature sensor.
(2) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR and VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430F5xx and MSP430F6xx Family User's Guide.
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
(4) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 vtemp_vs_temp.gifFigure 5-16 Typical Temperature Sensor Voltage