JAJSG45G May 2010 – September 2020 MSP430F5630 , MSP430F5631 , MSP430F5632 , MSP430F5633 , MSP430F5634 , MSP430F5635 , MSP430F5636 , MSP430F5637 , MSP430F5638
PRODUCTION DATA
The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. Table 9-12 lists the trigger assignments for each DMA channel.
The USB timestamp generator also uses the channel 0, 1, and 2 DMA trigger assignments.
TRIGGER(1) | CHANNEL | |||||
---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 4 | 5 | |
0 | DMAREQ | |||||
1 | TA0CCR0 CCIFG | |||||
2 | TA0CCR2 CCIFG | |||||
3 | TA1CCR0 CCIFG | |||||
4 | TA1CCR2 CCIFG | |||||
5 | TA2CCR0 CCIFG | |||||
6 | TA2CCR2 CCIFG | |||||
7 | TBCCR0 CCIFG | |||||
8 | TBCCR2 CCIFG | |||||
9 | Reserved | |||||
10 | Reserved | |||||
11 | Reserved | |||||
12 | Reserved | |||||
13 | Reserved | |||||
14 | Reserved | |||||
15 | Reserved | |||||
16 | UCA0RXIFG | |||||
17 | UCA0TXIFG | |||||
18 | UCB0RXIFG | |||||
19 | UCB0TXIFG | |||||
20 | UCA1RXIFG | |||||
21 | UCA1TXIFG | |||||
22 | UCB1RXIFG | |||||
23 | UCB1TXIFG | |||||
24 | ADC12IFGx(2) | |||||
25 | DAC12_0IFG(3) | |||||
26 | DAC12_1IFG(3) | |||||
27 | USB FNRXD | |||||
28 | USB ready | |||||
29 | MPY ready | |||||
30 | DMA5IFG | DMA0IFG | DMA1IFG | DMA2IFG | DMA3IFG | DMA4IFG |
31 | DMAE0 |