JAJSG45G May   2010  – September 2020 MSP430F5630 , MSP430F5631 , MSP430F5632 , MSP430F5633 , MSP430F5634 , MSP430F5635 , MSP430F5636 , MSP430F5637 , MSP430F5638

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O
    8. 8.8  Inputs – Ports P1, P2, P3, and P4
    9. 8.9  Leakage Current – General-Purpose I/O
    10. 8.10 Outputs – General-Purpose I/O (Full Drive Strength)
    11. 8.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
    12. 8.12 Output Frequency – Ports P1, P2, and P3
    13. 8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 8.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 8.16 Crystal Oscillator, XT2
    17. 8.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 8.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 8.19 DCO Frequency
    20. 8.20 PMM, Brownout Reset (BOR)
    21. 8.21 PMM, Core Voltage
    22. 8.22 PMM, SVS High Side
    23. 8.23 PMM, SVM High Side
    24. 8.24 PMM, SVS Low Side
    25. 8.25 PMM, SVM Low Side
    26. 8.26 Wake-up Times From Low-Power Modes and Reset
    27. 8.27 Timer_A, Timers TA0, TA1, and TA2
    28. 8.28 Timer_B, Timer TB0
    29. 8.29 Battery Backup
    30. 8.30 USCI (UART Mode)
    31. 8.31 USCI (SPI Master Mode)
    32. 8.32 USCI (SPI Slave Mode)
    33. 8.33 USCI (I2C Mode)
    34. 8.34 12-Bit ADC, Power Supply and Input Range Conditions
    35. 8.35 12-Bit ADC, Timing Parameters
    36. 8.36 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
    37. 8.37 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
    38. 8.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 8.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 8.40 REF, External Reference
    41. 8.41 REF, Built-In Reference
    42. 8.42 12-Bit DAC, Supply Specifications
    43. 8.43 12-Bit DAC, Linearity Specifications
    44. 8.44 12-Bit DAC, Output Specifications
    45. 8.45 12-Bit DAC, Reference Input Specifications
    46. 8.46 12-Bit DAC, Dynamic Specifications
    47. 8.47 12-Bit DAC, Dynamic Specifications (Continued)
    48. 8.48 Comparator_B
    49. 8.49 Ports PU.0 and PU.1
    50. 8.50 USB Output Ports DP and DM
    51. 8.51 USB Input Ports DP and DM
    52. 8.52 USB-PWR (USB Power System)
    53. 8.53 USB-PLL (USB Phase-Locked Loop)
    54. 8.54 Flash Memory
    55. 8.55 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Instruction Set
    4. 9.4  Operating Modes
    5. 9.5  Interrupt Vector Addresses
    6. 9.6  Memory
    7. 9.7  Bootloader (BSL)
      1. 9.7.1 USB BSL
      2. 9.7.2 UART BSL
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  Flash Memory
    10. 9.10 RAM
    11. 9.11 Backup RAM
    12. 9.12 Peripherals
      1. 9.12.1  Digital I/O
      2. 9.12.2  Port Mapping Controller
      3. 9.12.3  Oscillator and System Clock
      4. 9.12.4  Power-Management Module (PMM)
      5. 9.12.5  Hardware Multiplier (MPY) (Link to User's Guide)
      6. 9.12.6  Real-Time Clock (RTC_B)
      7. 9.12.7  Watchdog Timer (WDT_A)
      8. 9.12.8  System Module (SYS)
      9. 9.12.9  DMA Controller
      10. 9.12.10 Universal Serial Communication Interface (USCI)
      11. 9.12.11 Timer TA0
      12. 9.12.12 Timer TA1
      13. 9.12.13 Timer TA2
      14. 9.12.14 Timer TB0
      15. 9.12.15 Comparator_B
      16. 9.12.16 ADC12_A
      17. 9.12.17 DAC12_A
      18. 9.12.18 CRC16
      19. 9.12.19 Voltage Reference (REF) Module
      20. 9.12.20 USB Universal Serial Bus
      21. 9.12.21 Embedded Emulation Module (EEM)
      22. 9.12.22 Peripheral File Map
    13. 9.13 Input/Output Diagrams
      1. 9.13.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.13.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.13.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.13.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.13.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.13.6  Port P5 (P5.2 to P5.7) Input/Output With Schmitt Trigger
      7. 9.13.7  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      8. 9.13.8  Port P7 (P7.2) Input/Output With Schmitt Trigger
      9. 9.13.9  Port P7 (P7.3) Input/Output With Schmitt Trigger
      10. 9.13.10 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      11. 9.13.11 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      12. 9.13.12 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      13. 9.13.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports
      14. 9.13.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 9.13.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 9.14 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  サポート・リソース
    7. 10.7  Trademarks
    8. 10.8  静電気放電に関する注意事項
    9. 10.9  Export Control Notice
    10. 10.10 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.12.2 Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2. Table 9-9 lists the mnemonic for each function that can be assigned.

Table 9-9 Port Mapping Mnemonics and Functions
VALUEPxMAPy MNEMONICINPUT PIN FUNCTIONOUTPUT PIN FUNCTION
0PM_NONENoneDVSS
1PM_CBOUT–Comparator_B output
PM_TB0CLKTimer TB0 clock input–
2PM_ADC12CLK–ADC12CLK
PM_DMAE0DMAE0 Input–
3PM_SVMOUT–SVM output
PM_TB0OUTHTimer TB0 high-impedance input TB0OUTH–
4PM_TB0CCR0BTimer TB0 CCR0 capture input CCI0BTimer TB0: TB0.0 compare output Out0
5PM_TB0CCR1BTimer TB0 CCR1 capture input CCI1BTimer TB0: TB0.1 compare output Out1
6PM_TB0CCR2BTimer TB0 CCR2 capture input CCI2BTimer TB0: TB0.2 compare output Out2
7PM_TB0CCR3BTimer TB0 CCR3 capture input CCI3BTimer TB0: TB0.3 compare output Out3
8PM_TB0CCR4BTimer TB0 CCR4 capture input CCI4BTimer TB0: TB0.4 compare output Out4
9PM_TB0CCR5BTimer TB0 CCR5 capture input CCI5BTimer TB0: TB0.5 compare output Out5
10PM_TB0CCR6BTimer TB0 CCR6 capture input CCI6BTimer TB0: TB0.6 compare output Out6
11PM_UCA0RXDUSCI_A0 UART RXD (Direction controlled by USCI – input)
PM_UCA0SOMIUSCI_A0 SPI slave out master in (direction controlled by USCI)
12PM_UCA0TXDUSCI_A0 UART TXD (Direction controlled by USCI – output)
PM_UCA0SIMOUSCI_A0 SPI slave in master out (direction controlled by USCI)
13PM_UCA0CLKUSCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0STEUSCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
14PM_UCB0SOMIUSCI_B0 SPI slave out master in (direction controlled by USCI)
PM_UCB0SCLUSCI_B0 I2C clock (open drain and direction controlled by USCI)
15PM_UCB0SIMOUSCI_B0 SPI slave in master out (direction controlled by USCI)
PM_UCB0SDAUSCI_B0 I2C data (open drain and direction controlled by USCI)
16PM_UCB0CLKUSCI_B0 clock input/output (direction controlled by USCI)
PM_UCA0STEUSCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
17PM_MCLK–MCLK
18ReservedReserved for test purposes. Do not use this setting.
19ReservedReserved for test purposes. Do not use this setting.
20–30ReservedNoneDVSS
31 (0FFh)(1)PM_ANALOGDisables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are 5 bits wide, and the upper bits are ignored, which results in a maximum value of 31.

Table 9-10 lists the default values for all pins that support port mapping.

Table 9-10 Default Mapping
PINPxMAPy MNEMONICINPUT PIN FUNCTIONOUTPUT PIN FUNCTION
P2.0/P2MAP0PM_UCB0STE, PM_UCA0CLKUSCI_B0 SPI slave transmit enable (direction controlled by USCI – input),
USCI_A0 clock input/output (direction controlled by USCI)
P2.1/P2MAP1PM_UCB0SIMO, PM_UCB0SDAUSCI_B0 SPI slave in master out (direction controlled by USCI),
USCI_B0 I2C data (open drain and direction controlled by USCI)
P2.2/P2MAP2PM_UCB0SOMI, PM_UCB0SCLUSCI_B0 SPI slave out master in (direction controlled by USCI),
USCI_B0 I2C clock (open drain and direction controlled by USCI)
P2.3/P2MAP3PM_UCB0CLK, PM_UCA0STEUSCI_B0 clock input/output (direction controlled by USCI),
USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
P2.4/P2MAP4PM_UCA0TXD, PM_UCA0SIMOUSCI_A0 UART TXD (direction controlled by USCI – output),
USCI_A0 SPI slave in master out (direction controlled by USCI)
P2.5/P2MAP5PM_UCA0RXD, PM_UCA0SOMIUSCI_A0 UART RXD (direction controlled by USCI – input),
USCI_A0 SPI slave out master in (direction controlled by USCI)
P2.6/P2MAP6PM_NONE–DVSS
P2.7/P2MAP7PM_NONE–DVSS