JAJSG45G May 2010 – September 2020 MSP430F5630 , MSP430F5631 , MSP430F5632 , MSP430F5633 , MSP430F5634 , MSP430F5635 , MSP430F5636 , MSP430F5637 , MSP430F5638
PRODUCTION DATA
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage during program execution and flash programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 = DVCC = VCC)(1)(2) | PMMCOREVx = 0 | 1.8 | 3.6 | V | |
PMMCOREVx = 0, 1 | 2.0 | 3.6 | ||||
PMMCOREVx = 0, 1, 2 | 2.2 | 3.6 | ||||
PMMCOREVx = 0, 1, 2, 3 | 2.4 | 3.6 | ||||
VCC,USB | Supply voltage during USB operation, USB PLL disabled (USB_EN = 1, UPLLEN = 0) | PMMCOREVx = 0 | 1.8 | 3.6 | V | |
PMMCOREVx = 0, 1 | 2.0 | 3.6 | ||||
PMMCOREVx = 0, 1, 2 | 2.2 | 3.6 | ||||
PMMCOREVx = 0, 1, 2, 3 | 2.4 | 3.6 | ||||
Supply voltage during USB operation, USB PLL enabled(6) (USB_EN = 1, UPLLEN = 1) | PMMCOREVx = 2 | 2.2 | 3.6 | |||
PMMCOREVx = 2, 3 | 2.4 | 3.6 | ||||
VSS | Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 = DVSS2 = DVSS3 = VSS) | 0 | V | |||
VBAT,RTC | Backup-supply voltage with RTC operational | TA = 0°C to 85°C | 1.55 | 3.6 | V | |
TA = –40°C to +85°C | 1.70 | 3.6 | ||||
VBAT,MEM | Backup-supply voltage with backup memory retained | TA = –40°C to +85°C | 1.20 | 3.6 | V | |
TA | Operating free-air temperature | I version | –40 | 85 | °C | |
TJ | Operating junction temperature | I version | –40 | 85 | °C | |
CBAK | Capacitance at pin VBAK | 1 | 4.7 | 10 | nF | |
CVCORE | Capacitor at VCORE(4) | 470 | nF | |||
CDVCC/ CVCORE | Capacitor ratio of DVCC to VCORE | 10 | ||||
fSYSTEM | Processor frequency (maximum MCLK frequency)(3)(5) (see Figure 8-1) | PMMCOREVx = 0, 1.8 V ≤ VCC ≤ 3.6 V (default condition) | 0 | 8.0 | MHz | |
PMMCOREVx = 1, 2 V ≤ VCC ≤ 3.6 V | 0 | 12.0 | ||||
PMMCOREVx = 2, 2.2 V ≤ VCC ≤ 3.6 V | 0 | 16.0 | ||||
PMMCOREVx = 3, 2.4 V ≤ VCC ≤ 3.6 V | 0 | 20.0 | ||||
fSYSTEM_USB | Minimum processor frequency for USB operation | 1.5 | MHz | |||
USB_wait | Wait state cycles during USB operation | 16 | cycles |