JAJSG45 データシート

JAJSG45G May 2010 – September 2020 MSP430F5630 , MSP430F5631 , MSP430F5632 , MSP430F5633 , MSP430F5634 , MSP430F5635 , MSP430F5636 , MSP430F5637 , MSP430F5638

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

ZQW|113
- MPBG674
PZ|100
- MTQF013A

サーマルパッド・メカニカル・データ

PZ|100
- QFND428

発注情報

8.55 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_SBW	Spy-Bi-Wire input frequency	2.2 V, 3 V	0		20	MHz
t_SBW,Low	Spy-Bi-Wire low clock pulse duration	2.2 V, 3 V	0.025		15	µs
t_{SBW, En}	Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)⁽¹⁾	2.2 V, 3 V			1	µs
t_SBW,Rst	Spy-Bi-Wire return to normal operation time		15		100	µs
f_TCK	TCK input frequency (4-wire JTAG)⁽²⁾	2.2 V	0		5	MHz
f_TCK	TCK input frequency (4-wire JTAG)⁽²⁾	3 V	0		10	MHz
R_internal	Internal pulldown resistance on TEST	2.2 V, 3 V	45	60	80	kΩ

(1) Tools that access the Spy-Bi-Wire interface must wait for the t_SBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge.

(2) f_TCK may be restricted to meet the timing requirements of the module selected.