JAJSG46 データシート

JAJSG46F August 2010 – September 2020 MSP430F6433 , MSP430F6435 , MSP430F6436 , MSP430F6438

PRODUCTION DATA

8.34 USCI (I²C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8-15)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
f_USCI	USCI input clock frequency	Internal: SMCLK or ACLK, External: UCLK Duty cycle = 50% ±10%			f_SYSTEM	MHz
f_SCL	SCL clock frequency		2.2 V, 3 V	0	400	kHz
t_HD,STA	Hold time (repeated) START	f_SCL ≤ 100 kHz	2.2 V, 3 V	4.0		µs
t_HD,STA	Hold time (repeated) START	f_SCL > 100 kHz	2.2 V, 3 V	0.6		µs
t_SU,STA	Setup time for a repeated START	f_SCL ≤ 100 kHz	2.2 V, 3 V	4.7		µs
t_SU,STA	Setup time for a repeated START	f_SCL > 100 kHz	2.2 V, 3 V	0.6		µs
t_HD,DAT	Data hold time		2.2 V, 3 V	0		ns
t_SU,DAT	Data setup time		2.2 V, 3 V	250		ns
t_SU,STO	Setup time for STOP	f_SCL ≤ 100 kHz	2.2 V, 3 V	4.0		µs
t_SU,STO	Setup time for STOP	f_SCL > 100 kHz	2.2 V, 3 V	0.6		µs
t_SP	Pulse duration of spikes suppressed by input filter		2.2 V	50	600	ns
t_SP	Pulse duration of spikes suppressed by input filter		3 V	50	600	ns

Figure 8-15 I²C Mode Timing