JAJSG46F August   2010  – September 2020 MSP430F6433 , MSP430F6435 , MSP430F6436 , MSP430F6438

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 8.7  Thermal Resistance Characteristics
    8. 8.8  Schmitt-Trigger Inputs – General-Purpose I/O
    9. 8.9  Inputs – Ports P1, P2, P3, and P4
    10. 8.10 Leakage Current – General-Purpose I/O
    11. 8.11 Outputs – General-Purpose I/O (Full Drive Strength)
    12. 8.12 Outputs – General-Purpose I/O (Reduced Drive Strength)
    13. 8.13 Output Frequency – Ports P1, P2, and P3
    14. 8.14 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    15. 8.15 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    16. 8.16 Crystal Oscillator, XT1, Low-Frequency Mode
    17. 8.17 Crystal Oscillator, XT2
    18. 8.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 8.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 8.20 DCO Frequency
    21. 8.21 PMM, Brownout Reset (BOR)
    22. 8.22 PMM, Core Voltage
    23. 8.23 PMM, SVS High Side
    24. 8.24 PMM, SVM High Side
    25. 8.25 PMM, SVS Low Side
    26. 8.26 PMM, SVM Low Side
    27. 8.27 Wake-up Times From Low-Power Modes and Reset
    28. 8.28 Timer_A, Timers TA0, TA1, and TA2
    29. 8.29 Timer_B, Timer TB0
    30. 8.30 Battery Backup
    31. 8.31 USCI (UART Mode)
    32. 8.32 USCI (SPI Master Mode)
    33. 8.33 USCI (SPI Slave Mode)
    34. 8.34 USCI (I2C Mode)
    35. 8.35 LCD_B, Recommended Operating Conditions
    36. 8.36 LCD_B, Electrical Characteristics
    37. 8.37 12-Bit ADC, Power Supply and Input Range Conditions
    38. 8.38 12-Bit ADC, Timing Parameters
    39. 8.39 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
    40. 8.40 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
    41. 8.41 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    42. 8.42 12-Bit ADC, Temperature Sensor and Built-In VMID
    43. 8.43 REF, External Reference
    44. 8.44 REF, Built-In Reference
    45. 8.45 12-Bit DAC, Supply Specifications
    46. 8.46 12-Bit DAC, Linearity Specifications
    47. 8.47 12-Bit DAC, Output Specifications
    48. 8.48 12-Bit DAC, Reference Input Specifications
    49. 8.49 12-Bit DAC, Dynamic Specifications
    50. 8.50 12-Bit DAC, Dynamic Specifications (Continued)
    51. 8.51 Comparator_B
    52. 8.52 Ports PU.0 and PU.1
    53. 8.53 LDO-PWR (LDO Power System)
    54. 8.54 Flash Memory
    55. 8.55 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Instruction Set
    4. 9.4  Operating Modes
    5. 9.5  Interrupt Vector Addresses
    6. 9.6  Memory
    7. 9.7  Bootloader (BSL)
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  Flash Memory
    10. 9.10 RAM
    11. 9.11 Backup RAM
    12. 9.12 Peripherals
      1. 9.12.1  Digital I/O
      2. 9.12.2  Port Mapping Controller
      3. 9.12.3  Oscillator and System Clock
      4. 9.12.4  Power-Management Module (PMM)
      5. 9.12.5  Hardware Multiplier (MPY) (Link to User's Guide)
      6. 9.12.6  Real-Time Clock (RTC_B)
      7. 9.12.7  Watchdog Timer (WDT_A)
      8. 9.12.8  System Module (SYS)
      9. 9.12.9  DMA Controller
      10. 9.12.10 Universal Serial Communication Interface (USCI)
      11. 9.12.11 Timer TA0
      12. 9.12.12 Timer TA1
      13. 9.12.13 Timer TA2
      14. 9.12.14 Timer TB0
      15. 9.12.15 Comparator_B
      16. 9.12.16 ADC12_A
      17. 9.12.17 DAC12_A
      18. 9.12.18 CRC16
      19. 9.12.19 Voltage Reference (REF) Module
      20. 9.12.20 LCD_B
      21. 9.12.21 LDO and PU Port
      22. 9.12.22 Embedded Emulation Module (EEM)
      23. 9.12.23 Peripheral File Map
    13. 9.13 Input/Output Diagrams
      1. 9.13.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.13.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.13.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.13.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.13.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.13.6  Port P5 (P5.2 to P5.7) Input/Output With Schmitt Trigger
      7. 9.13.7  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      8. 9.13.8  Port P7 (P7.2) Input/Output With Schmitt Trigger
      9. 9.13.9  Port P7 (P7.3) Input/Output With Schmitt Trigger
      10. 9.13.10 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      11. 9.13.11 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      12. 9.13.12 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      13. 9.13.13 Port PU (PU.0 and PU.1) Ports
      14. 9.13.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 9.13.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 9.14 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  サポート・リソース
    7. 10.7  Trademarks
    8. 10.8  静電気放電に関する注意事項
    9. 10.9  Export Control Notice
    10. 10.10 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETERVCCPMMCOREVxTEMPERATURE (TA)UNIT
–40°C25°C60°C85°C
TYPMAXTYPMAXTYPMAXTYPMAX
ILPM0,1MHzLow-power mode 0(3)(9)2.2 V0717587818599µA
3 V37883988994108
ILPM2Low-power mode 2(4)(9)2.2 V06.36.79.99.01116µA
3 V36.67.011101218
ILPM3,XT1LFLow-power mode 3, crystal mode(5)(9)2.2 V01.61.82.44.76.510.5µA
11.61.94.86.6
21.72.04.96.7
3 V01.92.12.75.06.810.8
11.92.15.17.0
22.02.25.27.1
32.02.22.95.47.312.6
ILPM3, VLO,WDTLow-power mode 3, VLO mode, Watchdog enabled(6)(9)3 V00.91.21.94.05.910.3µA
10.91.24.16.0
21.01.34.26.1
31.01.32.24.36.311.3
ILPM4Low-power mode 4(7)(9)3 V00.91.11.83.95.810µA
10.91.14.05.9
21.01.24.16.1
31.01.22.14.26.211
ILPM3.5, RTC,VCCLow-power mode 3.5 (LPM3.5) current with active RTC into primary supply pin DVCC (10)3 V0.50.81.4µA
ILPM3.5, RTC,VBATLow-power mode 3.5 (LPM3.5) current with active RTC into backup supply pin VBAT(11)3 V0.60.81.4µA
ILPM3.5, RTC,TOTTotal low-power mode 3.5 (LPM3.5) current with active RTC(12)3 V1.01.11.31.62.8µA
ILPM4.5Low-power mode 4.5 (LPM4.5)(8)3 V0.20.30.60.70.91.4µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx  =  0).
CPUOFF  =  1, SCG0  =  0, SCG1  =  0, OSCOFF  =  0 (LPM0), fACLK =  32768 Hz, fMCLK = 0 MHz, fSMCLK  = fDCO  =  1 MHz
LDO disabled (LDOEN = 0).
(4) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx  =  0).
CPUOFF  =  1, SCG0  =  0, SCG1  =  1, OSCOFF  =  0 (LPM2), fACLK =  32768 Hz, fMCLK = 0 MHz, fSMCLK  = fDCO  =  0 MHz; DCO setting = 1 MHz operation, DCO bias generator enabled.
LDO disabled (LDOEN = 0).
(5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx  =  0).
CPUOFF  =  1, SCG0  =  1, SCG1  =  1, OSCOFF  =  0 (LPM3), fACLK =  32768 Hz, fMCLK = fSMCLK  = fDCO  =  0 MHz
LDO disabled (LDOEN = 0).
(6) Current for watchdog timer clocked by VLO included.
CPUOFF  =  1, SCG0  =  1, SCG1  =  1, OSCOFF  =  0 (LPM3), fACLK =  fMCLK = fSMCLK  =  fDCO  = 0 MHz
LDO disabled (LDOEN = 0).
(7) CPUOFF  =  1, SCG0  =  1, SCG1  =  1, OSCOFF  =  1 (LPM4), fDCO  = fACLK =  fMCLK  = fSMCLK  =  0 MHz
LDO disabled (LDOEN = 0).
(8) Internal regulator disabled. No data retention.
CPUOFF  =  1, SCG0  =  1, SCG1  =  1, OSCOFF  =  1, PMMREGOFF = 1 (LPM4.5), fDCO  = fACLK =  fMCLK  = fSMCLK  =  0 MHz
(9) Current for brownout included. Low-side supervisor (SVSL) and low-side monitor (SVML) disabled. High-side supervisor (SVSH) and high-side monitor (SVMH) disabled. RAM retention enabled.
(10) VVBAT = VCC – 0.2 V, fDCO  =  fMCLK  = fSMCLK  =  0 MHz, fACLK  =  32768 Hz, PMMREGOFF  = 1, RTC in backup domain active
(11) VVBAT = VCC – 0.2 V, fDCO  =  fMCLK  = fSMCLK  =  0 MHz, fACLK  =  32768 Hz, PMMREGOFF  = 1, RTC in backup domain active, no current drawn on VBAK
(12) fDCO  = fMCLK  =  fSMCLK  =  0 MHz, fACLK  =  32768 Hz, PMMREGOFF  =  1, RTC in backup domain active, no current drawn on VBAK