JAJSBT6E October   2012  – September 2020 MSP430F5358 , MSP430F5359 , MSP430F5658 , MSP430F5659 , MSP430F6458 , MSP430F6459 , MSP430F6658 , MSP430F6659

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 8.7  Thermal Resistance Characteristics
    8. 8.8  Schmitt-Trigger Inputs – General-Purpose I/O
    9. 8.9  Inputs – Ports P1, P2, P3, and P4
    10. 8.10 Leakage Current – General-Purpose I/O
    11. 8.11 Outputs – General-Purpose I/O (Full Drive Strength)
    12. 8.12 Outputs – General-Purpose I/O (Reduced Drive Strength)
    13. 8.13 Output Frequency – Ports P1, P2, and P3
    14. 8.14 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    15. 8.15 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    16. 8.16 Crystal Oscillator, XT1, Low-Frequency Mode
    17. 8.17 Crystal Oscillator, XT2
    18. 8.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    19. 8.19 Internal Reference, Low-Frequency Oscillator (REFO)
    20. 8.20 DCO Frequency
    21. 8.21 PMM, Brownout Reset (BOR)
    22. 8.22 PMM, Core Voltage
    23. 8.23 PMM, SVS High Side
    24. 8.24 PMM, SVM High Side
    25. 8.25 PMM, SVS Low Side
    26. 8.26 PMM, SVM Low Side
    27. 8.27 Wake-up Times From Low-Power Modes
    28. 8.28 Timer_A – Timers TA0, TA1, and TA2
    29. 8.29 Timer_B – Timer TB0
    30. 8.30 Battery Backup
    31. 8.31 USCI (UART Mode)
    32. 8.32 USCI (SPI Master Mode)
    33. 8.33 USCI (SPI Slave Mode)
    34. 8.34 USCI (I2C Mode)
    35. 8.35 LCD_B Operating Characteristics
    36. 8.36 LCD_B Electrical Characteristics
    37. 8.37 12-Bit ADC, Power Supply and Input Range Conditions
    38. 8.38 12-Bit ADC, Timing Parameters
    39. 8.39 12-Bit ADC, Linearity Parameters Using an External Reference Voltage
    40. 8.40 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
    41. 8.41 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    42. 8.42 12-Bit ADC, Temperature Sensor and Built-In VMID
    43. 8.43 REF, External Reference
    44. 8.44 REF, Built-In Reference
    45. 8.45 12-Bit DAC, Supply Specifications
    46. 8.46 12-Bit DAC, Linearity Specifications
    47. 8.47 12-Bit DAC, Output Specifications
    48. 8.48 12-Bit DAC, Reference Input Specifications
    49. 8.49 12-Bit DAC, Dynamic Specifications
    50. 8.50 12-Bit DAC, Dynamic Specifications (Continued)
    51. 8.51 Comparator_B
    52. 8.52 Ports PU.0 and PU.1
    53. 8.53 USB Output Ports DP and DM
    54. 8.54 USB Input Ports DP and DM
    55. 8.55 USB-PWR (USB Power System)
    56. 8.56 USB-PLL (USB Phase Locked Loop)
    57. 8.57 Flash Memory
    58. 8.58 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Instruction Set
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Memory Organization
    6. 9.6  Bootloader (BSL)
      1. 9.6.1 USB BSL
      2. 9.6.2 UART BSL
    7. 9.7  JTAG Operation
      1. 9.7.1 JTAG Standard Interface
      2. 9.7.2 Spy-Bi-Wire Interface
    8. 9.8  Flash Memory
    9. 9.9  Memory Integrity Detection (MID)
    10. 9.10 RAM
    11. 9.11 Backup RAM
    12. 9.12 Peripherals
      1. 9.12.1  Digital I/O
      2. 9.12.2  Port Mapping Controller
      3. 9.12.3  Oscillator and System Clock
      4. 9.12.4  Power-Management Module (PMM)
      5. 9.12.5  Hardware Multiplier (MPY)
      6. 9.12.6  Real-Time Clock (RTC_B)
      7. 9.12.7  Watchdog Timer (WDT_A)
      8. 9.12.8  System Module (SYS)
      9. 9.12.9  DMA Controller
      10. 9.12.10 Universal Serial Communication Interface (USCI)
      11. 9.12.11 Timer TA0
      12. 9.12.12 Timer TA1
      13. 9.12.13 Timer TA2
      14. 9.12.14 Timer TB0
      15. 9.12.15 Comparator_B
      16. 9.12.16 ADC12_A
      17. 9.12.17 DAC12_A
      18. 9.12.18 CRC16
      19. 9.12.19 Voltage Reference (REF) Module
      20. 9.12.20 LCD_B
      21. 9.12.21 USB Universal Serial Bus
      22. 9.12.22 LDO and PU Port
      23. 9.12.23 Embedded Emulation Module (EEM) (L Version)
      24. 9.12.24 Peripheral File Map
    13. 9.13 Input/Output Diagrams
      1. 9.13.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.13.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.13.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.13.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.13.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.13.6  Port P5 (P5.2 to P5.7) Input/Output With Schmitt Trigger
      7. 9.13.7  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      8. 9.13.8  Port P7 (P7.2) Input/Output With Schmitt Trigger
      9. 9.13.9  Port P7 (P7.3) Input/Output With Schmitt Trigger
      10. 9.13.10 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      11. 9.13.11 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      12. 9.13.12 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      13. 9.13.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports (F665x, F565x)
      14. 9.13.14 Port PU (PU.0 and PU.1) Ports (F645x, F535x)
      15. 9.13.15 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      16. 9.13.16 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 9.14 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  Community Resources
    7. 10.7  Trademarks
    8. 10.8  静電気放電に関する注意事項
    9. 10.9  Export Control Notice
    10. 10.10 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Revision History

Changed from revision D to revision E

Changes from September 27, 2018 to September 11, 2020

  • 文書全体にわたってセクション、表、図、相互参照の採番方法を更新Go
  • 文書全体にわたって nFBGA パッケージ (ZCA) の情報を追加Go
  • 「表 3-1」の ZQW パッケージの注文可能なすべての部品番号のステータスの変更に関する注を追加Go
  • Removed package options that are no longer available (MSP430F6658 and MSP430F6458 in the ZQW package) in Table 6-1, Device Comparison Go
  • Removed packge options that are no longer available (MSP430F6658IZQW and MSP430F6458IZQW) from the caption of Figure 7-5, 113-Pin ZQW Package (Top View) – MSP430F6659IZQW, MSP430F6459IZQW, MSP430F5659IZQW, MSP430F5658IZQW, MSP430F5359IZQW, MSP430F5358IZQW Go
  • Changed the MAX value of the IERASE and IMERASE, IBANK parameters in Section 8.57, Flash Memory Go
  • Corrected the connection of the P7SEL.x signal in Figure 9-11, Port P7 (P7.4 to P7.7) Diagram Go

Changes from revision C to revision D

Changes from October 22, 2013 to September 26, 2018

  • 文書全体にわたってフォーマットと構成を変更、セクションの番号追加も含むGo
  • 「製品情報」表を追加Go
  • Section 4を追加し、すべての機能ブロック図をこのセクションに移動Go
  • Added Section 6.1, Related Products Go
  • Added "Port U is supplied the LDOO rail" to the description of PU.0 and PU.1 in Section 7.2, Signal Descriptions Go
  • Added Section 8 and moved all electrical specifications to itGo
  • Added typical conditions statements at the beginning of Section 8, Specifications Go
  • Added Section 8.2, ESD Ratings Go
  • Moved Section 8.7, Thermal Resistance Characteristics Go
  • Changed the TYP value of the CL,eff parameter with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF in Section 8.16, Crystal Oscillator, XT1, Low-Frequency Mode Go
  • Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Section 8.21, PMM, Brownout Reset (BOR) Go
  • Updated notes (1) and (2) and added note (3) in Section 8.27, Wake-up Times From Low-Power Modes and Reset Go
  • Corrected typo in the description of the VBAT3 parameter: changed "VBAT3 ≠ VBAT/3" to "VBAT3 ≈ VBAT/3" in Section 8.30, Battery Backup Go
  • Removed ADC12DIV from the formula for the TYP value in the second row of the tCONVERT parameter in Section 8.38, 12-Bit ADC, Timing Parameters, because ADC12CLK is after divisionGo
  • Added the TCSENSOR parameter in Section 8.42, 12-Bit ADC, Temperature Sensor and Built-In VMID Go
  • Changed the note that starts "The temperature sensor offset ..." from "...offset can be as much as ±20°C" to "...offset can be significant"Go
  • Changed DAC12xDAT to DAC12_xDAT in IL(DAC12) Test Conditions in Section 8.47, 12-Bit DAC, Output Specifications Go
  • Removed note from "Ri(VREF+), Ri(VeREF+)" parameter in Section 8.48, 12-Bit DAC, Reference Input Specifications Go
  • Changed from fDAC12_0OUT to fDAC12_1OUT in the first row of the Test Conditions for the "Channel-to-channel crosstalk" parameter in Section 8.50, 12-Bit DAC, Dynamic Specifications (Continued) Go
  • Changed the value of DAC12_xDAT from 7F7h to F7Fh and changed the x-axis label from fToggle to 1/fToggle in Figure 8-22, Crosstalk Test Conditions Go
  • Section 8.51, Comparator_B: Added second row for the tEN_CMP parameter with Test Conditions of "CBPWRMD = 10" and MAX value of 100 µs; Removed "CBPWRMD = 10" option in first row of Test ConditionsGo
  • Added note on RPUR in Section 8.55, USB-PWR (USB Power System) Go
  • Removed RTC_B from LPM4.5 wake-up options in Section 9.3, Operating Modes Go
  • Throughout document, changed "bootstrap loader" to "bootloader"Go
  • Added the paragraph that begins "Using the MSP430 RTC_B Module With Battery Backup Supply describes how to..." Go
  • Corrected spelling of NMIIFG in Table 9-12, System Module Interrupt Vector Registers Go
  • Corrected register names (added "USB" prefix as required) in Table 9-53, USB Control Registers Go
  • Added P7SEL.2 and XT2BYPASS inputs with AND and OR gates in Figure 9-10, Port P7 (P7.3) Diagram Go
  • Changed P7SEL.3 column from X to 0 for "P7.3 (I/O)" rows in Table 9-63, Port P7 (P7.2 and P7.3) Pin Functions Go
  • Updated Table 9-67, Port PU.0, PU.1 Functions Go
  • Added Section 9.13.14, Port PU.0, PU.1 Ports (F645x, F535x) Go
  • Added Section 10, Device and Documentation Support, and moved Development Tools Support, Device and Development Tool Nomenclature, Trademarks, and Electrostatic Discharge Caution sections to itGo
  • Replaced former section Development Tools Support with Section 10.3, Tools and Software Go
  • Added Section 11, Mechanical, Packaging, and Orderable Information Go

The following table lists changes to this data sheet from the original release to revision C.

REVISION COMMENTS
SLAS700C October 2013

Added Section 1

Removed Ordering Information table—refer to the Package Option Addendum

Table 1-1, Corrected Interrupt Event names for PMMSWBOR (BOR) and PMMSWPOR (POR)

Table 1-3, Added PM5CTL0 register

Section 1, Added note to CVCORE

Section 1, Added note to RPull

Section 1, Corrected VIL and VIH limits
SLAS700B June 2013

Ordering Information, Corrected package type for PZ package (LQFP)

Changed functional block diagrams

Table 1-1, Added note to the RST/NMI/SBWTDIO pin

Added Development Tools Support and Device and Development Tool Nomenclature

Section 1, Fixed typo in fSYSTEM conditions

Section 1, Added note (1)
SLAS700A December 2012 PRODUCTION DATA release
SLAS700 October 2012 PRODUCT PREVIEW release

Changes from Revision () to Revision ()