JAJSCD5A August   2016  – August 2016 MSP430F6459-HIREL

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Schmitt-Trigger Inputs - General-Purpose I/O
    8. 5.8  Leakage Current - General-Purpose I/O
    9. 5.9  Outputs - General-Purpose I/O (Full Drive Strength)
    10. 5.10 Outputs - General-Purpose I/O (Reduced Drive Strength)
    11. 5.11 Thermal Resistance Characteristics for PZ Package
    12. 5.12 Typical Characteristics - Outputs, Reduced Drive Strength (PxDS.y = 0)
    13. 5.13 Typical Characteristics - Outputs, Full Drive Strength (PxDS.y = 1)
    14. 5.14 Timing and Switching Characteristics
      1. 5.14.1 Power Supply Sequencing
      2. 5.14.2 Clock Specifications
      3. 5.14.3 Peripherals
      4. 5.14.4 Emulation and Debug
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Instruction Set
    4. 6.4  Operating Modes
    5. 6.5  Interrupt Vector Addresses
    6. 6.6  Memory Organization
    7. 6.7  Bootloader (BSL)
      1. 6.7.1 UART BSL
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire Interface
    9. 6.9  Flash Memory
    10. 6.10 Memory Integrity Detection (MID)
    11. 6.11 RAM
    12. 6.12 Backup RAM
    13. 6.13 Peripherals
      1. 6.13.1  Digital I/O
      2. 6.13.2  Port Mapping Controller
      3. 6.13.3  Oscillator and System Clock
      4. 6.13.4  Power-Management Module (PMM)
      5. 6.13.5  Hardware Multiplier (MPY)
      6. 6.13.6  Real-Time Clock (RTC_B)
      7. 6.13.7  Watchdog Timer (WDT_A)
      8. 6.13.8  System Module (SYS)
      9. 6.13.9  DMA Controller
      10. 6.13.10 Universal Serial Communication Interface (USCI)
      11. 6.13.11 Timer TA0
      12. 6.13.12 Timer TA1
      13. 6.13.13 Timer TA2
      14. 6.13.14 Timer TB0
      15. 6.13.15 Comparator_B
      16. 6.13.16 ADC12_A
      17. 6.13.17 DAC12_A
      18. 6.13.18 CRC16
      19. 6.13.19 Voltage Reference (REF) Module
      20. 6.13.20 LCD_B
      21. 6.13.21 LDO and PU Port
      22. 6.13.22 Embedded Emulation Module (EEM) (L Version)
      23. 6.13.23 Peripheral File Map
    14. 6.14 Input/Output Schematics
      1. 6.14.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.14.2  Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
      3. 6.14.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
      4. 6.14.4  Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
      5. 6.14.5  Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
      6. 6.14.6  Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger
      7. 6.14.7  Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
      8. 6.14.8  Port P7, P7.2, Input/Output With Schmitt Trigger
      9. 6.14.9  Port P7, P7.3, Input/Output With Schmitt Trigger
      10. 6.14.10 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      11. 6.14.11 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      12. 6.14.12 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      13. 6.14.13 Port PU.0, PU.1 Ports
      14. 6.14.14 Port J, PJ.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 6.14.15 Port J, PJ.1 to PJ.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    15. 6.15 Device Descriptors
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 General Layout Recommendations
      6. 7.1.6 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  使い始めと次の手順
    2. 8.2  Device Nomenclature
    3. 8.3  ツールとソフトウェア
      1. 8.3.1 ハードウェアの特長
      2. 8.3.2 推奨ハードウェア・オプション
        1. 8.3.2.1 ターゲット・ソケット基板
        2. 8.3.2.2 検証用基板
        3. 8.3.2.3 デバッグおよびプログラミングのツール
        4. 8.3.2.4 量産プログラマ
      3. 8.3.3 推奨ソフトウェア・オプション
        1. 8.3.3.1 統合開発環境
        2. 8.3.3.2 MSP430Ware
        3. 8.3.3.3 TI-RTOS
        4. 8.3.3.4 コマンドライン・プログラマ
    4. 8.4  ドキュメントのサポート
    5. 8.5  ドキュメントの更新通知を受け取る方法
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 用語集
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Specifications

5.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage applied at VCC to VSS –0.3 4.1 V
Voltage applied to any pin (excluding VCORE, VBUS, V18)(2) –0.3 VCC + 0.3 V
Diode current at any device pin ±2 mA
Maximum junction temperature, TJ –40 105 °C
Storage temperature, Tstg(3) –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance.

5.3 Recommended Operating Conditions

Typical values are specified at VCC = 3.3 V and TJ = 25°C (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage during program execution and flash programming (AVCC1  =  DVCC1 = DVCC2 = DVCC3  = DVCC = VCC)(1)(2) PMMCOREVx = 0 1.8 3.6 V
PMMCOREVx = 0, 1 2 3.6
PMMCOREVx = 0, 1, 2 2.2 3.6
PMMCOREVx = 0, 1, 2, 3 2.4 3.6
VSS Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 = DVSS2 = DVSS3  =  VSS) 0 V
VBAT,RTC Backup-supply voltage with RTC operational TJ = –40°C to 105°C 1.7 3.6 V
VBAT,MEM Backup-supply voltage with backup memory retained TJ = –40°C to 105°C 1.2 3.6 V
TJ Operating junction temperature T version –40 105 °C
CBAK Capacitance at pin VBAK 1 4.7 10 nF
CVCORE Capacitor at VCORE(3) 470 nF
CDVCC / CVCORE Capacitor ratio of DVCC to VCORE 10
fSYSTEM Processor frequency (maximum MCLK frequency)(4)(5) (see Figure 5-1) PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V (default condition)		 0 8 MHz
PMMCOREVx = 1,
2 V ≤ VCC ≤ 3.6 V		 0 12
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V		 0 16
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V		 0 20
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Table 5-11 threshold parameters for the exact values and further details.
(3) A capacitor tolerance of ±20% or better is required.
(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the specified maximum frequency.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
MSP430F6459-HIREL slas566-op_cond.gif Figure 5-1 Frequency vs Supply Voltage

5.4 Active Mode Supply Current Into VCC Excluding External Current

over recommended operating junction temperature (unless otherwise noted)(1) (2) (3)
PARAMETER EXECUTION MEMORY VCC PMMCOREVx FREQUENCY (fDCO = fMCLK = fSMCLK) UNIT
1 MHz 8 MHz 12 MHz 20 MHz
TYP MAX TYP MAX TYP MAX TYP MAX
IAM, Flash Flash 3 V 0 0.36 0.45 2.4 2.7 mA
1 0.41 2.7 4.0 4.4
2 0.46 2.9 4.3
3 0.51 3.1 4.5 7.4
IAM, RAM RAM 3 V 0 0.18 0.25 1.0 1.3 mA
1 0.20 1.2 1.7 1.9
2 0.22 1.3 2.0
3 0.23 1.4 2.2 3.6
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.

5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)(1) (2)
PARAMETER VCC PMMCOREVx –40°C 25°C 60°C 105°C UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
ILPM0,1MHz Low-power mode 0(3) (9) 2.2 V 0 69 73 95 79 101 135 µA
3 V 3 79 83 120 87 116 155
ILPM2 Low-power mode 2(4) (9) 2.2 V 0 6.1 6.7 9.0 8.0 22 40 µA
3 V 3 6.5 7.1 9.5 8.5 24 42
ILPM3,XT1LF Low-power mode 3, crystal mode(5) (9) 2.2 V 0 1.5 2.0 3.3 3.3 18 34 µA
1 1.7 2.2 3.6 8.5
2 1.9 2.4 3.8 18.7
3 V 0 1.8 2.2 3.5 3.6 18.3 35
1 1.9 2.4 3.8 18.7
2 2.1 2.6 4.0 18.8
3 2.1 2.6 4.2 4.0 19.4 37
ILPM3,VLO, WDT Low-power mode 3, VLO mode, Watchdog enabled(6) (9) 3 V 0 1.0 1.3 2.7 2.7 17.2 34 µA
1 1.1 1.5 2.8 17.5
2 1.1 1.6 2.9 17.6
3 1.1 1.6 3.2 2.9 18.2 35
ILPM4 Low-power mode 4(7) (9) 3 V 0 0.9 1.3 2.5 2.5 17.1 34 µA
1 1.0 1.3 2.6 17.3
2 1.0 1.4 2.7 17.5
3 1.0 1.4 3.1 2.7 18 36
ILPM3.5,RTC,VCC Low-power mode 3.5 (LPM3.5) current with active RTC into primary supply pin DVCC (10) 3 V 0.5 1.25 2.3 µA
ILPM3.5,RTC,VBAT Low-power mode 3.5 (LPM3.5) current with active RTC into backup supply pin VBAT(11) 3 V 0.6 0.78 1.3 µA
ILPM3.5,RTC,TOT Total Low-power mode 3.5 (LPM3.5) current with active RTC(12) 3 V 1.0 1.1 1.2 1.93 3.3 µA
ILPM4.5 Low-power mode 4.5(8) 3 V 0.4 0.45 0.6 0.5 1.21 2.4 µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx  =  0).
CPUOFF  =  1, SCG0  =  0, SCG1  =  0, OSCOFF  =  0 (LPM0), fACLK  =  32768 Hz, fMCLK = 0 MHz, fSMCLK  =  fDCO  =  1 MHz
(4) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx  =  0).
CPUOFF  =  1, SCG0  =  0, SCG1  =  1, OSCOFF  =  0 (LPM2), fACLK  =  32768 Hz, fMCLK = 0 MHz, fSMCLK  =  fDCO  =  0 MHz, DCO setting = 1 MHz operation, DCO bias generator enabled.
(5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx  =  0).
CPUOFF  =  1, SCG0  =  1, SCG1  =  1, OSCOFF  =  0 (LPM3), fACLK  =  32768 Hz, fMCLK = fSMCLK  =  fDCO  =  0 MHz
(6) Current for watchdog timer clocked by VLO included.
CPUOFF  =  1, SCG0  =  1, SCG1  =  1, OSCOFF  =  0 (LPM3), fACLK  =  fMCLK = fSMCLK  =  fDCO  =  0 MHz
(7) CPUOFF  =  1, SCG0  =  1, SCG1  =  1, OSCOFF  =  1 (LPM4), fDCO  = fACLK =  fMCLK  =  fSMCLK  =  0 MHz
(8) Internal regulator disabled. No data retention.
CPUOFF  =  1, SCG0  =  1, SCG1  =  1, OSCOFF  =  1, PMMREGOFF = 1 (LPM4.5), fDCO  = fACLK =  fMCLK  =  fSMCLK  =  0 MHz
(9) Current for brownout included. Low-side supervisor and monitors disabled (SVSL, SVML). High-side supervisor and monitor disabled (SVSH, SVMH). RAM retention enabled.
(10) VVBAT = VCC - 0.2 V, fDCO  =  fMCLK  =  fSMCLK  =  0 MHz, fACLK  =  32768 Hz, PMMREGOFF  =  1, RTC in backup domain active
(11) VVBAT = VCC - 0.2 V, fDCO  =  fMCLK  =  fSMCLK  =  0 MHz, fACLK  =  32768 Hz, PMMREGOFF  =  1, RTC in backup domain active, no current drawn on VBAK
(12) fDCO  =  fMCLK  =  fSMCLK  =  0 MHz, fACLK  =  32768 Hz, PMMREGOFF  =  1, RTC in backup domain active, no current drawn on VBAK

5.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)(1)(2)
PARAMETER VCC PMMCOREVx TEMPERATURE (TJ) UNIT
–40°C 25°C 60°C 105°C
TYP MAX TYP MAX TYP MAX TYP MAX
ILPM3 LCD, int. bias Low-power mode 3 (LPM3) current, LCD 4-mux mode, internal biasing, charge pump disabled(1) (2) 3 V 0 2.7 3.3 4.8 4.7 18.3 35 µA
1 2.9 3.5 5.0 18.7
2 3.0 3.7 5.2 19
3 3.1 3.7 5.3 5.2 19.3 37
ILPM3 LCD,CP Low-power mode 3 (LPM3) current, LCD 4-mux mode, internal biasing, charge pump enabled(1) (3) 2.2 V 0 3.6 µA
1 3.7
2 4.0
3 V 0 3.5
1 3.7
2 3.8
3 3.9
(1) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx  =  0).
CPUOFF  =  1, SCG0  =  1, SCG1  =  1, OSCOFF  =  0 (LPM3), fACLK  =  32768 Hz, fMCLK = fSMCLK  =  fDCO  =  0 MHz
Current for brownout included. Low-side supervisor (SVSL) and low-side monitor (SVML) disabled. High-side supervisor (SVSH) and high-side monitor (SVMH) disabled. RAM retention enabled.
(2) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
(3) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump enabled), VLCDx = 1000 (VLCD = 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.

5.7 Schmitt-Trigger Inputs – General-Purpose I/O(1)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VIT+ Positive-going input threshold voltage 1.8 V 0.80 1.40 V
3 V 1.50 2.10
VIT– Negative-going input threshold voltage 1.8 V 0.45 1.00 V
3 V 0.75 1.65
Vhys Input voltage hysteresis (VIT+ – VIT–) 1.8 V 0.3 0.8 V
3 V 0.4 1.0
RPull Pullup or pulldown resistor(2) For pullup: VIN = VSS
For pulldown: VIN = VCC 		20 35 50 kΩ
CI Input capacitance VIN = VSS or VCC 5 pF
(1) The same parametrics apply to the clock input pin when the crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
(2) Also applies to RST pin when pullup or pulldown resistor is enabled.

5.8 Leakage Current – General-Purpose I/O

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(Px.y) High-impedance leakage current  (1)(2) 1.8 V, 3 V ±50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.

5.9 Outputs – General-Purpose I/O (Full Drive Strength)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VOH High-level output voltage I(OHmax) = –3 mA(1) 1.8 V VCC – 0.25 VCC V
I(OHmax) = –10 mA(2) VCC – 0.60 VCC
I(OHmax) = –5 mA(1) 3 V VCC – 0.25 VCC
I(OHmax) = –15 mA(2) VCC – 0.60 VCC
VOL Low-level output voltage I(OLmax) = 3 mA(1) 1.8 V VSS VSS + 0.25 V
I(OLmax) = 10 mA(2) VSS VSS + 0.60
I(OLmax) = 5 mA(1) 3 V VSS VSS + 0.25
I(OLmax) = 15 mA(2) VSS VSS + 0.60
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.

5.10 Outputs – General-Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)(3)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VOH High-level output voltage I(OHmax) = –1 mA(1) 1.8 V VCC – 0.25 VCC V
I(OHmax) = –3 mA(2) VCC – 0.60 VCC
I(OHmax) = –2 mA(1) 3 V VCC – 0.25 VCC
I(OHmax) = –6 mA(2) VCC – 0.60 VCC
VOL Low-level output voltage I(OLmax) = 1 mA(1) 1.8 V VSS VSS + 0.25 V
I(OLmax) = 3 mA(2) VSS VSS + 0.60
I(OLmax) = 2 mA(1) 3 V VSS VSS + 0.25
I(OLmax) = 6 mA(2) VSS VSS + 0.60
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified.
(3) Selecting reduced drive strength may reduce EMI.

5.11 Thermal Resistance Characteristics for PZ Package

PARAMETER PACKAGE VALUE UNIT
θJA Junction-to-ambient thermal resistance, still air(1) QFP (PZ) 122 °C/W
θJC(TOP) Junction-to-case (top) thermal resistance(2) QFP (PZ) 83 °C/W
θJB Junction-to-board thermal resistance(3) QFP (PZ) 98 °C/W
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

5.12 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

MSP430F6459-HIREL slas566-005.gif
VCC = 3 V
Figure 5-2 Typical Low-Level Output Current vs Low-Level Output Voltage
MSP430F6459-HIREL slas566-007.gif
VCC = 3 V
Figure 5-4 Typical High-Level Output Current vs High-Level Output Voltage
MSP430F6459-HIREL slas566-006.gif
VCC = 1.8 V
Figure 5-3 Typical Low-Level Output Current vs Low-Level Output Voltage
MSP430F6459-HIREL slas566-008.gif
VCC = 1.8 V
Figure 5-5 Typical High-Level Output Current vs High-Level Output Voltage

5.13 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)

MSP430F6459-HIREL slas566-009.gif
VCC = 3 V
Figure 5-6 Typical Low-Level Output Current vs Low-Level Output Voltage
MSP430F6459-HIREL slas566-011.gif
VCC = 3 V
Figure 5-8 Typical High-Level Output Current vs High-Level Output Voltage
MSP430F6459-HIREL slas566-010.gif
VCC = 1.8 V
Figure 5-7 Typical Low-Level Output Current vs Low-Level Output Voltage
MSP430F6459-HIREL slas566-012.gif
VCC = 1.8 V
Figure 5-9 Typical High-Level Output Current vs High-Level Output Voltage

5.14 Timing and Switching Characteristics

5.14.1 Power Supply Sequencing

TI recommends powering the AVCC and DVCC pins from the same source. At a minimum, during power up, power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits specified in the Absolute Maximum Ratings section. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.

Table 5-1 PMM, Brownout Reset (BOR)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(DVCC_BOR_IT–) BORH on voltage, DVCC falling level | dDVCC/dt | < 3 V/s 1.45 V
V(DVCC_BOR_IT+) BORH off voltage, DVCC rising level | dDVCC/dt | < 3 V/s 0.80 1.30 1.50 V
V(DVCC_BOR_hys) BORH hysteresis 60 250 mV
tRESET Pulse duration required at RST/NMI pin to accept a reset 2 µs

5.14.2 Clock Specifications

Table 5-2 Inputs – Ports P1, P2, P3, and P4(1)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
t(int) External interrupt timing(2) Port P1, P2, P3, P4: P1.x to P4.x, External trigger pulse duration to set interrupt flag 2.2 V, 3 V 20 ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int).

Table 5-3 Output Frequency – Ports P1, P2, and P3

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
fPx.y Port output frequency (with load) P3.4/TA2CLK/SMCLK/S27,
CL = 20 pF, RL = 1 kΩ (1) or 3.2 kΩ(2) (3) 		VCC = 1.8 V,
PMMCOREVx = 0		 8 MHz
VCC = 3 V,
PMMCOREVx = 3		 20
fPort_CLK Clock output frequency P1.0/TA0CLK/ACLK/S39,
P3.4/TA2CLK/SMCLK/S27,
P2.0/P2MAP0 (P2MAP0 = PM_MCLK),
CL = 20 pF(3)		 VCC = 1.8 V,
PMMCOREVx = 0		 8 MHz
VCC = 3 V,
PMMCOREVx = 3		 20
(1) Full drive strength of port: A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
(2) Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
(3) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

Table 5-4 Crystal Oscillator, XT1, Low-Frequency Mode(5)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
ΔIDVCC,LF Differential XT1 oscillator crystal current consumption from lowest drive setting, LF mode fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1, TJ = 25°C		 3 V 0.075 µA
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2, TJ = 25°C		 0.170
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3, TJ = 25°C		 0.290
fXT1,LF0 XT1 oscillator crystal frequency, LF mode XTS = 0, XT1BYPASS = 0 32768 Hz
fXT1,LF,SW XT1 oscillator logic-level square-wave input frequency, LF mode XTS = 0, XT1BYPASS = 1(6) (7) 10 32.768 50 kHz
OALF Oscillation allowance for LF crystals(8) XTS = 0, XT1BYPASS  =  0, XT1DRIVEx  =  0,
fXT1,LF  =  32768 Hz, CL,eff  =  6 pF, TJ = 25°C		 3 V 210 kΩ
XTS = 0, XT1BYPASS  =  0, XT1DRIVEx  =  1,
fXT1,LF  =  32768 Hz, CL,eff  =  12 pF, TJ = 25°C		 300
CL,eff Integrated effective load capacitance, LF mode(1) XTS = 0, XCAPx = 0(2) 1 pF
XTS = 0, XCAPx = 1 5.5
XTS = 0, XCAPx = 2 8.5
XTS = 0, XCAPx = 3 12.0
Duty cycle, LF mode XTS = 0, Measured at ACLK,
fXT1,LF  =  32768 Hz		 30% 70%
fFault,LF Oscillator fault frequency, LF mode(4) XTS = 0(3) 10 10000 Hz
tSTART,LF Start-up time, LF mode fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TJ = 25°C, CL,eff  =  6 pF		 3 V 1000 ms
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TJ = 25°C, CL,eff  =  12 pF		 500
(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.
(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(3) Measured with logic-level input frequency but also applies to operation with crystals.
(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag.
(5) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
  • Keep the trace between the device and the crystal as short as possible.
  • Design a good ground plane around the oscillator pins.
  • Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
  • Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
  • Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
  • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(6) When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this data sheet.
(7) Maximum frequency of operation of the entire device cannot be exceeded.
(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application:
  • For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
  • For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
  • For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
  • For XT1DRIVEx = 3, CL,eff ≥ 6 pF.

Table 5-5 Crystal Oscillator, XT2

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)(2) (5)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IDVCC,XT2 XT2 oscillator crystal current consumption fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0, TJ = 25°C		 3 V 200 µA
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1, TJ = 25°C		 260
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2, TJ = 25°C		 325
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3, TJ = 25°C		 450
fXT2,HF0 XT2 oscillator crystal frequency, mode 0 XT2DRIVEx = 0, XT2BYPASS = 0(7) 4 8 MHz
fXT2,HF1 XT2 oscillator crystal frequency, mode 1 XT2DRIVEx = 1, XT2BYPASS = 0(7) 8 16 MHz
fXT2,HF2 XT2 oscillator crystal frequency, mode 2 XT2DRIVEx = 2, XT2BYPASS = 0(7) 16 24 MHz
fXT2,HF3 XT2 oscillator crystal frequency, mode 3 XT2DRIVEx = 3, XT2BYPASS = 0(7) 24 32 MHz
fXT2,HF,SW XT2 oscillator logic-level square-wave input frequency XT2BYPASS = 1(6) (7) 0.7 32 MHz
OAHF Oscillation allowance for HF crystals(8) XT2DRIVEx  =  0, XT2BYPASS  =  0,
fXT2,HF0  =  6 MHz, CL,eff  =  15 pF, TJ = 25°C		 3 V 450 Ω
XT2DRIVEx  =  1, XT2BYPASS  =  0,
fXT2,HF1  =  12 MHz, CL,eff  =  15 pF, TJ = 25°C		 320
XT2DRIVEx  =  2, XT2BYPASS  =  0,
fXT2,HF2  =  20 MHz, CL,eff  =  15 pF, TJ = 25°C		 200
XT2DRIVEx  =  3, XT2BYPASS  =  0,
fXT2,HF3  =  32 MHz, CL,eff  =  15 pF, TJ = 25°C		 200
tSTART,HF Start-up time fOSC = 6 MHz, XT2BYPASS = 0, XT2DRIVEx = 0,
TJ = 25°C, CL,eff  =  15 pF		 3 V 0.5 ms
fOSC = 20 MHz, XT2BYPASS = 0, XT2DRIVEx = 3,
TJ = 25°C, CL,eff  =  15 pF		 0.3
CL,eff Integrated effective load capacitance, HF mode(1) (2) 1 pF
Duty cycle Measured at ACLK, fXT2,HF2  =  20 MHz 40% 50% 60%
fFault,HF Oscillator fault frequency(4) XT2BYPASS = 1(3) 30 300 kHz
(1) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.
(2) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(3) Measured with logic-level input frequency but also applies to operation with crystals.
(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag.
(5) To improve EMI on the XT2 oscillator the following guidelines should be observed.
  • Keep the traces between the device and the crystal as short as possible.
  • Design a good ground plane around the oscillator pins.
  • Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
  • Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
  • Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
  • If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(6) When XT2BYPASS is set, the XT2 circuit is automatically powered down.
(7) Maximum frequency of operation of the entire device cannot be exceeded.
(8) Oscillation allowance is based on a safety factor of 5 for recommended crystals.

Table 5-6 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V 6 9.4 14 kHz
dfVLO/dT VLO frequency temperature drift Measured at ACLK(1) 1.8 V to 3.6 V 0.5 %/°C
dfVLO/dVCC VLO frequency supply voltage drift Measured at ACLK(2) 1.8 V to 3.6 V 4 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40% 50% 60%
(1) Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Table 5-7 Internal Reference, Low-Frequency Oscillator (REFO)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IREFO REFO oscillator current consumption TJ = 25°C 1.8 V to 3.6 V 3 µA
fREFO REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Hz
REFO absolute tolerance calibrated Full temperature range 1.8 V to 3.6 V ±3.5%
TJ = 25°C 3 V ±1.5%
dfREFO/dT REFO frequency temperature drift Measured at ACLK(1) 1.8 V to 3.6 V 0.01 %/°C
dfREFO/dVCC REFO frequency supply voltage drift Measured at ACLK(2) 1.8 V to 3.6 V 1.0 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40% 50% 60%
tSTART REFO start-up time 40%/60% duty cycle 1.8 V to 3.6 V 25 µs
(1) Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C) / (105°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)

Table 5-8 DCO Frequency

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fDCO(0,0) DCO frequency (0, 0)(1) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz
fDCO(0,31) DCO frequency (0, 31)(1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz
fDCO(1,0) DCO frequency (1, 0)(1) DCORSELx = 1, DCOx = 0, MODx = 0 0.15 0.36 MHz
fDCO(1,31) DCO frequency (1, 31)(1) DCORSELx = 1, DCOx = 31, MODx = 0 1.47 3.45 MHz
fDCO(2,0) DCO frequency (2, 0)(1) DCORSELx = 2, DCOx = 0, MODx = 0 0.32 0.75 MHz
fDCO(2,31) DCO frequency (2, 31)(1) DCORSELx = 2, DCOx = 31, MODx = 0 3.17 7.38 MHz
fDCO(3,0) DCO frequency (3, 0)(1) DCORSELx = 3, DCOx = 0, MODx = 0 0.64 1.51 MHz
fDCO(3,31) DCO frequency (3, 31)(1) DCORSELx = 3, DCOx = 31, MODx = 0 6.07 14.0 MHz
fDCO(4,0) DCO frequency (4, 0)(1) DCORSELx = 4, DCOx = 0, MODx = 0 1.3 3.2 MHz
fDCO(4,31) DCO frequency (4, 31)(1) DCORSELx = 4, DCOx = 31, MODx = 0 12.3 28.2 MHz
fDCO(5,0) DCO frequency (5, 0)(1) DCORSELx = 5, DCOx = 0, MODx = 0 2.5 6.0 MHz
fDCO(5,31) DCO frequency (5, 31)(1) DCORSELx = 5, DCOx = 31, MODx = 0 23.7 54.1 MHz
fDCO(6,0) DCO frequency (6, 0)(1) DCORSELx = 6, DCOx = 0, MODx = 0 4.6 10.7 MHz
fDCO(6,31) DCO frequency (6, 31)(1) DCORSELx = 6, DCOx = 31, MODx = 0 39.0 88.0 MHz
fDCO(7,0) DCO frequency (7, 0)(1) DCORSELx = 7, DCOx = 0, MODx = 0 8.5 19.6 MHz
fDCO(7,31) DCO frequency (7, 31)(1) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz
SDCORSEL Frequency step between range DCORSEL and DCORSEL + 1 SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratio
SDCO Frequency step between tap DCO and DCO + 1 SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratio
Duty cycle Measured at SMCLK 40% 50% 60%
dfDCO/dT DCO frequency temperature drift fDCO = 1 MHz, 0.1 %/°C
dfDCO/dVCC DCO frequency voltage drift fDCO = 1 MHz 1.9 %/V
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency, range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31 (DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the selected range is at its minimum or maximum tap setting.
MSP430F6459-HIREL slas566-dco.gif Figure 5-10 Typical DCO Frequency

Table 5-9 Wake-Up Times From Low-Power Modes

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tWAKE-UP-FAST Wake-up time from LPM2, LPM3, or LPM4 to active mode(1) PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1,
fMCLK ≥ 4.0 MHz		 3 6.5 µs
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1,
1 MHz < fMCLK < 4.0 MHz		 4 8.0
tWAKE-UP-SLOW Wake-up time from LPM2, LPM3 or LPM4 to active mode(2) PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0		 150 165
tWAKE-UP LPM5 Wake-up time from LPM3.5 or LPM4.5 to active mode(3) 2 3 ms
tWAKE-UP-RESET Wake-up time from RST or BOR event to active mode(3) 2 3 ms
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). Fastest wake-up times are possible with SVSL and SVML in full-performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSL and SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). In this case, the SVSL and SVML are in normal mode (low current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVSL and SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
(3) This value represents the time from the wake-up event to the reset vector execution.

5.14.3 Peripherals

Table 5-10 PMM, Core Voltage

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCORE3(AM) Core voltage, active mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA 1.90 V
VCORE2(AM) Core voltage, active mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA 1.80 V
VCORE1(AM) Core voltage, active mode, PMMCOREV = 1 2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 17 mA 1.60 V
VCORE0(AM) Core voltage, active mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 13 mA 1.40 V
VCORE3(LPM) Core voltage, low-current mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA 1.94 V
VCORE2(LPM) Core voltage, low-current mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA 1.84 V
VCORE1(LPM) Core voltage, low-current mode, PMMCOREV = 1 2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA 1.64 V
VCORE0(LPM) Core voltage, low-current mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA 1.44 V

Table 5-11 PMM, SVS High Side

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(SVSH) SVS current consumption SVSHE = 0, DVCC = 3.6 V 0 nA
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 200
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 2.0 µA
V(SVSH_IT–) SVSH on voltage level(1) SVSHE = 1, SVSHRVL = 0 1.59 1.64 1.69 V
SVSHE = 1, SVSHRVL = 1 1.79 1.84 1.91
SVSHE = 1, SVSHRVL = 2 1.98 2.04 2.11
SVSHE = 1, SVSHRVL = 3 2.10 2.16 2.23
V(SVSH_IT+) SVSH off voltage level(1) SVSHE = 1, SVSMHRRL = 0 1.62 1.74 1.81 V
SVSHE = 1, SVSMHRRL = 1 1.88 1.94 2.01
SVSHE = 1, SVSMHRRL = 2 2.07 2.14 2.21
SVSHE = 1, SVSMHRRL = 3 2.20 2.26 2.33
SVSHE = 1, SVSMHRRL = 4 2.32 2.40 2.48
SVSHE = 1, SVSMHRRL = 5 2.56 2.70 2.84
SVSHE = 1, SVSMHRRL = 6 2.85 3.00 3.15
SVSHE = 1, SVSMHRRL = 7 2.85 3.00 3.15
tpd(SVSH) SVSH propagation delay SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 2.5 µs
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 20
t(SVSH) SVSH on or off delay time SVSHE = 0→1, SVSHFP = 1 12.5 µs
SVSHE = 0→1, SVSHFP = 0 100
dVDVCC/dt DVCC rise time 0 1000 V/s
(1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.

Table 5-12 PMM, SVM High Side

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(SVMH) SVMH current consumption SVMHE = 0, DVCC = 3.6 V 0 nA
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 200
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 2.0 µA
V(SVMH) SVMH on or off voltage level(1) SVMHE = 1, SVSMHRRL = 0 1.65 1.74 1.86 V
SVMHE = 1, SVSMHRRL = 1 1.85 1.94 2.02
SVMHE = 1, SVSMHRRL = 2 2.02 2.14 2.22
SVMHE = 1, SVSMHRRL = 3 2.18 2.26 2.35
SVMHE = 1, SVSMHRRL = 4 2.32 2.40 2.48
SVMHE = 1, SVSMHRRL = 5 2.56 2.70 2.84
SVMHE = 1, SVSMHRRL = 6 2.85 3.00 3.15
SVMHE = 1, SVSMHRRL = 7 2.85 3.00 3.15
SVMHE = 1, SVMHOVPE = 1 3.75
tpd(SVMH) SVMH propagation delay SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 2.5 µs
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 20
t(SVMH) SVMH on or off delay time SVMHE = 0→1, SVSMFP = 1 12.5 µs
SVMHE = 0→1, SVMHFP = 0 100
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage.

Table 5-13 PMM, SVS Low Side

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(SVSL) SVSL current consumption SVSLE = 0, PMMCOREV = 2 0 nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 2.0 µA
tpd(SVSL) SVSL propagation delay SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 2.5 µs
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 20
t(SVSL) SVSL on or off delay time SVSLE = 0→1, SVSLFP = 1 12.5 µs
SVSLE = 0→1, SVSLFP = 0 100

Table 5-14 PMM, SVM Low Side

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(SVML) SVML current consumption SVMLE = 0, PMMCOREV = 2 0 nA
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 200
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 2.0 µA
tpd(SVML) SVML propagation delay SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP  =  1 2.5 µs
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP  =  0 20
t(SVML) SVML on or off delay time SVMLE = 0→1, SVMLFP = 1 12.5 µs
SVMLE = 0→1, SVMLFP = 0 100

Table 5-15 Timer_A – Timers TA0, TA1, and TA2

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
fTA Timer_A input clock frequency Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ±10%		 1.8 V, 3 V 20 MHz
tTA,cap Timer_A capture timing All capture inputs, Minimum pulse duration required for capture 1.8 V, 3 V 20 ns

Table 5-16 Timer_B – Timer TB0

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
fTB Timer_B input clock frequency Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ±10%		 1.8 V, 3 V 20 MHz
tTB,cap Timer_B capture timing All capture inputs, Minimum pulse duration required for capture 1.8 V, 3 V 20 ns

Table 5-17 Battery Backup

over operating junction temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IVBAT Current into VBAT terminal if no primary battery is connected VBAT = 1.7 V,
DVCC not connected,
RTC running		 TJ = –40°C 0.43 µA
TJ = 25°C 0.52
TJ = 60°C 0.58
TJ = 105°C 0.66
VBAT = 2.2 V,
DVCC not connected,
RTC running		 TJ = –40°C 0.50
TJ = 25°C 0.59
TJ = 60°C 0.64
TJ = 105°C 0.72
VBAT = 3 V,
DVCC not connected,
RTC running		 TJ = –40°C 0.68
TJ = 25°C 0.75
TJ = 60°C 0.79
TJ = 105°C 0.87
VSWITCH Switch-over level (VCC to VBAT) CVCC = 4.7 µF General VSVSH_IT- V
SVSHRL = 0 1.59 1.69
SVSHRL = 1 1.79 1.91
SVSHRL = 2 1.98 2.11
SVSHRL = 3 2.10 2.23
RON_VBAT On-resistance of switch between VBAT and VBAK VBAT = 1.8 V 0 V 0.35 1 kΩ
VBAT3 VBAT to ADC input channel 12:
VBAT divided, VBAT3 ≈ VBAT/3 		1.8 V 0.6 ±5% V
3 V 1.0 ±5%
3.6 V 1.2 ±5%
tSample, VBAT3 VBAT to ADC: Sampling time required if VBAT3 selected ADC12ON = 1,
Error of conversion result ≤ 2 LSB		 1000 ns
VCHVx Charger end voltage CHVx = 2 2.65 2.7 2.9 V
RCHARGE Charge limiting resistor CHCx = 1 5.2 kΩ
CHCx = 2 10.2
CHCx = 3 20

Table 5-18 USCI (UART Mode)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fUSCI USCI input clock frequency Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%		 fSYSTEM MHz
fBITCLK BITCLK clock frequency
(equals baud rate in MBaud)		 1 MHz
tτ UART receive deglitch time(1) 2.2 V 50 600 ns
3 V 50 600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time.

Table 5-19 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)(1)
(see Figure 5-11 and )
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fUSCI USCI input clock frequency SMCLK or ACLK,
Duty cycle = 50% ±10%		 fSYSTEM MHz
tSU,MI SOMI input data setup time PMMCOREV = 0 1.8 V 55 ns
3 V 38
PMMCOREV = 3 2.4 V 30
3 V 25
tHD,MI SOMI input data hold time PMMCOREV = 0 1.8 V 0 ns
3 V 0
PMMCOREV = 3 2.4 V 0
3 V 0
tVALID,MO SIMO output data valid time(2) UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0		 1.8 V 20 ns
3 V 18
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3		 2.4 V 16
3 V 15
tHD,MO SIMO output data hold time(3) CL = 20 pF, PMMCOREV = 0 1.8 V –10 ns
3 V –8
CL = 20 pF, PMMCOREV = 3 2.4 V –10
3 V –8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-11 and Figure 5-12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-11 and Figure 5-12.
MSP430F6459-HIREL slas566-013.gif Figure 5-11 SPI Master Mode, CKPH = 0
MSP430F6459-HIREL slas566-014.gif Figure 5-12 SPI Master Mode, CKPH = 1

Table 5-20 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)(1)
(see Figure 5-13 and Figure 5-14)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
tSTE,LEAD STE lead time, STE low to clock PMMCOREV = 0 1.8 V 11 ns
3 V 8
PMMCOREV = 3 2.4 V 7
3 V 6
tSTE,LAG STE lag time, last clock to STE high PMMCOREV = 0 1.8 V 1 ns
3 V 1
PMMCOREV = 3 2.4 V 1
3 V 1
tSTE,ACC STE access time, STE low to SOMI data out PMMCOREV = 0 1.8 V 66 ns
3 V 50
PMMCOREV = 3 2.4 V 36
3 V 30
tSTE,DIS STE disable time, STE high to SOMI high impedance PMMCOREV = 0 1.8 V 30 ns
3 V 30
PMMCOREV = 3 2.4 V 30
3 V 30
tSU,SI SIMO input data setup time PMMCOREV = 0 1.8 V 5 ns
3 V 5
PMMCOREV = 3 2.4 V 2
3 V 2
tHD,SI SIMO input data hold time PMMCOREV = 0 1.8 V 5 ns
3 V 5
PMMCOREV = 3 2.4 V 5
3 V 5
tVALID,SO SOMI output data valid time(2) UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 0		 1.8 V 76 ns
3 V 60
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 3		 2.4 V 44
3 V 40
tHD,SO SOMI output data hold time(3) CL = 20 pF, PMMCOREV = 0 1.8 V 12 ns
3 V 12
CL = 20 pF, PMMCOREV = 3 2.4 V 12
3 V 12
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 and Figure 5-14.
MSP430F6459-HIREL slas566-015.gif Figure 5-13 SPI Slave Mode, CKPH = 0
MSP430F6459-HIREL slas566-016.gif Figure 5-14 SPI Slave Mode, CKPH = 1

Table 5-21 USCI (I2C Mode)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted) (see Figure 5-15)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fUSCI USCI input clock frequency Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ±10%		 fSYSTEM MHz
fSCL SCL clock frequency 2.2 V, 3 V 0 400 kHz
tHD,STA Hold time (repeated) START fSCL ≤ 100 kHz 2.2 V, 3 V 4.0 µs
fSCL > 100 kHz 0.6
tSU,STA Setup time for a repeated START fSCL ≤ 100 kHz 2.2 V, 3 V 4.7 µs
fSCL > 100 kHz 0.6
tHD,DAT Data hold time 2.2 V, 3 V 0 ns
tSU,DAT Data setup time 2.2 V, 3 V 250 ns
tSU,STO Setup time for STOP fSCL ≤ 100 kHz 2.2 V, 3 V 4.0 µs
fSCL > 100 kHz 0.6
tSP Pulse duration of spikes suppressed by input filter 2.2 V 50 600 ns
3 V 50 600
MSP430F6459-HIREL slas566-017.gif Figure 5-15 I2C Mode Timing

Table 5-22 LCD_B Operating Characteristics

over operating junction temperature range (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
VCC,LCD_B,CP en,3.6 Supply voltage range, charge pump enabled, VLCD ≤ 3.6 V LCDCPEN = 1, 0000 < VLCDx ≤ 1111 (charge pump enabled, VLCD ≤ 3.6 V) 2.2 3.6 V
VCC,LCD_B,CP en,3.3 Supply voltage range, charge pump enabled, VLCD ≤ 3.3 V LCDCPEN = 1, 0000 < VLCDx ≤ 1100 (charge pump enabled, VLCD ≤ 3.3 V) 2.0 3.6 V
VCC,LCD_B,int. bias Supply voltage range, internal biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V
VCC,LCD_B,ext. bias Supply voltage range, external biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 0 2.4 3.6 V
VCC,LCD_B,VLCDEXT Supply voltage range, external LCD voltage, internal or external biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 1 2.0 3.6 V
VLCDCAP/R33 External LCD voltage at LCDCAP/R33, internal or external biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 1 2.4 3.6 V
CLCDCAP Capacitor on LCDCAP when charge pump enabled LCDCPEN = 1, VLCDx > 0000 (charge pump enabled) 4.7 10 µF
fFrame LCD frame frequency range fLCD = 2 × mux × fFRAME with mux = 1 (static), 2, 3, 4 0 100 Hz
fACLK,in ACLK input frequency range 30 32 40 kHz
CPanel Panel capacitance 100-Hz frame frequency 10000 pF
VR33 Analog input voltage at R33 LCDCPEN = 0, VLCDEXT = 1 2.4 VCC + 0.2 V
VR23,1/3bias Analog input voltage at R23 LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 VR13 VR03 + 2/3 × (VR33 – VR03) VR33 V
VR13,1/3bias Analog input voltage at R13 with 1/3 biasing LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 VR03 VR03 + 1/3 × (VR33 – VR03) VR23 V
VR13,1/2bias Analog input voltage at R13 with 1/2 biasing LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 1 VR03 VR03 + 1/2 × (VR33 – VR03) VR33 V
VR03 Analog input voltage at R03 R0EXT = 1 VSS V
VLCD-VR03 Voltage difference between VLCD and R03 LCDCPEN = 0, R0EXT = 1 2.4 VCC + 0.2 V
VLCDREF/R13 External LCD reference voltage applied at LCDREF/R13 VLCDREFx = 01 0.8 1.2 1.5 V

Table 5-23 LCD_B Electrical Characteristics

over operating junction temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VLCD LCD voltage VLCDx = 0000, VLCDEXT = 0 2.4 V to 3.6 V VCC V
LCDCPEN = 1, VLCDx = 0001 2 V to 3.6 V 2.59
LCDCPEN = 1, VLCDx = 0010 2 V to 3.6 V 2.66
LCDCPEN = 1, VLCDx = 0011 2 V to 3.6 V 2.72
LCDCPEN = 1, VLCDx = 0100 2 V to 3.6 V 2.79
LCDCPEN = 1, VLCDx = 0101 2 V to 3.6 V 2.85
LCDCPEN = 1, VLCDx = 0110 2 V to 3.6 V 2.92
LCDCPEN = 1, VLCDx = 0111 2 V to 3.6 V 2.98
LCDCPEN = 1, VLCDx = 1000 2 V to 3.6 V 3.05
LCDCPEN = 1, VLCDx = 1001 2 V to 3.6 V 3.10
LCDCPEN = 1, VLCDx = 1010 2 V to 3.6 V 3.17
LCDCPEN = 1, VLCDx = 1011 2 V to 3.6 V 3.24
LCDCPEN = 1, VLCDx = 1100 2 V to 3.6 V 3.30
LCDCPEN = 1, VLCDx = 1101 2.2 V to 3.6 V 3.36
LCDCPEN = 1, VLCDx = 1110 2.2 V to 3.6 V 3.42
LCDCPEN = 1, VLCDx = 1111 2.2 V to 3.6 V 3.48 3.6
ICC,Peak,CP Peak supply currents due to charge pump activities LCDCPEN = 1, VLCDx = 1111 2.2 V 400 µA
tLCD,CP,on Time to charge CLCD when discharged CLCD = 4.7 µF, LCDCPEN = 0→1, VLCDx = 1111 2.2 V 100 500 ms
ICP,Load Maximum charge pump load current LCDCPEN = 1, VLCDx = 1111 2.2 V 50 µA
RLCD,Seg LCD driver output impedance, segment lines LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA		 2.2 V 10 kΩ
RLCD,COM LCD driver output impedance, common lines LCDCPEN = 1, VLCDx = 1000,
ILOAD = ±10 µA		 2.2 V 10 kΩ

Table 5-24 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)(2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V		 2.2 3.6 V
V(Ax) Analog input voltage range(3) All ADC12 analog input pins Ax 0 AVCC V
IADC12_A Operating supply current into AVCC terminal(4) fADC12CLK = 5.0 MHz(1) 2.2 V 150 200 µA
3 V 150 250
CI Input capacitance Only one terminal Ax can be selected at one time 2.2 V 20 25 pF
RI Input MUX ON resistance 0 V ≤ VIN ≤ V(AVCC) 10 200 1900 Ω
(1) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV =  0
(2) The leakage current is specified by the digital I/O input leakage.
(3) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the reference voltage is supplied by an external source or if the internal voltage is used and REFOUT = 1, then decoupling capacitors are required. See Table 5-30 and Table 5-31.
(4) The internal reference supply current is not included in current consumption parameter IADC12.

Table 5-25 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fADC12CLK ADC conversion clock For specified performance of ADC12 linearity parameters using an external reference voltage or AVCC as reference(1) 2.2 V, 3 V 0.45 4.8 5.0 MHz
For specified performance of ADC12 linearity parameters using the internal reference(2) 0.45 2.4 4.0
For specified performance of ADC12 linearity parameters using the internal reference(3) 0.45 2.4 2.7
fADC12OSC Internal ADC12 oscillator(6) ADC12DIV = 0, fADC12CLK = fADC12OSC 2.2 V, 3 V 4.2 4.8 5.4 MHz
tCONVERT Conversion time REFON = 0, Internal oscillator,
ADC12OSC used for ADC conversion clock		 2.2 V, 3 V 2.4 3.1 µs
External fADC12CLK from ACLK, MCLK or SMCLK, ADC12SSEL ≠ 0 See (5)
tSample Sampling time RS = 400 Ω, RI = 200 Ω, CI = 20 pF,
τ = [RS + RI] × CI (4) 		2.2 V, 3 V 1000 ns
(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0, SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5.0 MHz.
(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC divided by 2.
(4) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
(5) 13 × ADC12DIV × 1/fADC12CLK
(6) The ADC12OSC is sourced directly from MODOSC inside the UCS.

Table 5-26 12-Bit ADC, Linearity Parameters Using an External Reference Voltage

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
EI Integral linearity error(2) 1.4 V ≤ dVREF ≤ 1.6 V(1) 2.2 V, 3 V ±2 LSB
1.6 V < dVREF (1) ±1.7
ED Differential linearity error(2) See (1) 2.2 V, 3 V ±1 LSB
EO Offset error(3) dVREF ≤ 2.2 V(1) 2.2 V, 3 V ±3 ±5.6 LSB
dVREF > 2.2 V(1) 2.2 V, 3 V ±1.5 ±3.5
EG Gain error(3) See (1) 2.2 V, 3 V ±1 ±2.5 LSB
ET Total unadjusted error dVREF ≤ 2.2 V(1) 2.2 V, 3 V ±3.5 ±7.1 LSB
dVREF > 2.2 V(1) 2.2 V, 3 V ±2 ±5
(1) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ – VR–. VR+ < AVCC. VR– > AVSS. Unless otherwise mentioned dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω and two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current. See also the MSP430F5xx and MSP430F6xx Family User's Guide (SLAU208).
(2) Parameters are derived using the histogram method.
(3) Parameters are derived using a best fit curve.

Table 5-27 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
EI Integral linearity error(2) See (1) 2.2 V, 3 V ±2.0 LSB
ED Differential linearity error(2) See (1) 2.2 V, 3 V ±1 LSB
EO Offset error(3) See (1) 2.2 V, 3 V ±1 ±2 LSB
EG Gain error(3) See (1) 2.2 V, 3 V ±2 ±4 LSB
ET Total unadjusted error See (1) 2.2 V, 3 V ±2 ±5 LSB
(1) AVCC as reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 0.
(2) Parameters are derived using the histogram method.
(3) Parameters are derived using a best fit curve.

Table 5-28 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) VCC MIN TYP MAX UNIT
EI Integral linearity error(2) ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz 2.2 V, 3 V ±2.0 LSB
ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz ±2.5
ED Differential linearity error(2) ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz 2.2 V, 3 V –1 +1.5 LSB
ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 2.7 MHz ±1
ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz –1 +2.5
EO Offset error(3) ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz 2.2 V, 3 V ±2 ±4 LSB
ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz ±2 ±4
EG Gain error(3) ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz 2.2 V, 3 V ±1 ±2.5 LSB
ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz ±1%(4) VREF
ET Total unadjusted error ADC12SR = 0, REFOUT = 1 fADC12CLK ≤ 4.0 MHz 2.2 V, 3 V ±2 ±5 LSB
ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 2.7 MHz ±1%(4) VREF
(1) The external reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 1. dVREF = VR+ – VR–.
(2) Parameters are derived using the histogram method.
(3) Parameters are derived using a best fit curve.
(4) The gain error and the total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this mode, the reference voltage used by the ADC12_A is not available on a pin.

Table 5-29 12-Bit ADC, Temperature Sensor and Built-In VMID(1)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VSENSOR See Figure 5-16(2) ADC12ON = 1, INCH = 0Ah, TJ = 0°C 2.2 V 680 mV
3 V 680
tSENSOR(sample) Sample time required if channel 10 is selected(3) ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB		 2.2 V 30 µs
3 V 30
VMID AVCC divider at channel 11 ADC12ON = 1, INCH = 0Bh,
VMID ≈ 0.5 × VAVCC 		2.2 V 1.06 1.1 1.14 V
3 V 1.46 1.5 1.54
tVMID(sample) Sample time required if channel 11 is selected(4) ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB		 2.2 V, 3 V 1000 ns
(1) The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of the temperature sensor.
(2) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 105°C ±3°C for each of the available reference voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR and VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430F5xx and MSP430F6xx Family User's Guide (SLAU208).
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
(4) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
MSP430F6459-HIREL vtemp_vs_temp.gif Figure 5-16 Typical Temperature Sensor Voltage

Table 5-30 REF, External Reference

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VeREF+ Positive external reference voltage input VeREF+ > VREF–/VeREF– (2) 1.4 AVCC V
VREF–/VeREF– Negative external reference voltage input VeREF+ > VREF–/VeREF– (3) 0 1.2 V
(VeREF+ –
VREF–/VeREF–)		 Differential external reference voltage input VeREF+ > VREF–/VeREF– (4) 1.4 AVCC V
IVeREF+, IVREF–/VeREF– Static input current 1.4 V ≤ VeREF+ ≤ VAVCC, VeREF–  = 0 V,
fADC12CLK = 5 MHz, ADC12SHTx = 1h,
Conversion rate 200 ksps		 2.2 V, 3 V –32 32 µA
1.4 V ≤ VeREF+ ≤ VAVCC , VeREF–  = 0 V,
fADC12CLK = 5 MHZ, ADC12SHTx = 8h,
Conversion rate 20 ksps 		2.2 V, 3 V –1.2 +1.2
CVREF+/- Capacitance at VREF+ or VREF- terminal(5) 10 µF
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).

Table 5-31 REF, Built-In Reference

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF+ Positive built-in reference voltage output REFVSEL = {2} for 2.5 V,
REFON = REFOUT = 1, IVREF+ = 0 A		 3 V 2.5 ±1% V
REFVSEL = {1} for 2 V,
REFON = REFOUT = 1, IVREF+ = 0 A		 3 V 2.0 ±1%
REFVSEL = {0} for 1.5 V,
REFON = REFOUT = 1, IVREF+ = 0 A		 2.2 V, 3 V 1.5 ±1%
AVCC(min) AVCC minimum voltage, Positive built-in reference active REFVSEL = {0} for 1.5 V 2.2 V
REFVSEL = {1} for 2 V 2.3
REFVSEL = {2} for 2.5 V 2.8
IREF+ Operating supply current into AVCC terminal (2) (7) ADC12SR = 1(8),
REFON = 1, REFOUT = 0, REFBURST = 0		 3 V 70 100 µA
ADC12SR = 1(8),
REFON = 1, REFOUT = 1, REFBURST = 0		 0.45 0.75 mA
ADC12SR = 0(8),
REFON = 1, REFOUT = 0, REFBURST = 0		 210 310 µA
ADC12SR = 0(8),
REFON = 1, REFOUT = 1, REFBURST = 0		 0.95 1.7 mA
IL(VREF+) Load-current regulation, VREF+ terminal(3) REFVSEL = {0, 1, 2},
IVREF+ = +10 µA or –1000 µA,
AVCC = AVCC(min) for each reference level,
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1		 1500 2500 µV/mA
CVREF+ Capacitance at VREF+ terminal REFON = REFOUT = 1(6),
0 mA ≤ IVREF+ ≤ IVREF+(max)		 2.2 V, 3 V 20 100 pF
TCREF+ Temperature coefficient of built-in reference(4) IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ –1 mA		 REFOUT = 0 2.2 V, 3 V 20 ppm/ °C
TCREF+ Temperature coefficient of built-in reference(4) IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ –1 mA		 REFOUT = 1 2.2 V, 3 V 20 50 ppm/ °C
PSRR_DC Power supply rejection ratio (DC) AVCC = AVCC(min) to AVCC(max), TJ = 25°C,
REFVSEL = {0, 1, 2}, REFON = 1,
REFOUT = 0 or 1		 120 300 µV/V
PSRR_AC Power supply rejection ratio (AC) AVCC = AVCC(min) to AVCC(max), TJ = 25°C,
REFVSEL = {0, 1, 2}, REFON = 1,
REFOUT = 0 or 1		 1 mV/V
tSETTLE Settling time of reference voltage(5) AVCC = AVCC(min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFOUT = 0,
REFON = 0 → 1		 75 µs
AVCC = AVCC(min) to AVCC(max),
CVREF = CVREF(max), REFVSEL = {0, 1, 2},
REFOUT = 1, REFON = 0 → 1		 75
(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal and is used as the reference for the conversion and uses the larger buffer. When REFOUT = 0, the reference is only used as the reference for the conversion and uses the smaller buffer.
(2) The internal reference current is supplied from the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless a conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current contribution of the larger buffer without external load.
(3) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace or other causes.
(4) Calculated using the box method: (MAX(–40°C to 105°C) – MIN(–40°C to 105°C)) / MIN(–40°C to 105°C)/(105°C – (–40°C)).
(5) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external capacitive load when REFOUT = 1.
(6) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
(7) The temperature sensor is provided by the REF module. Its current is supplied from the AVCC terminal and is equivalent to IREF+ with REFON = 1 and REFOUT = 0.
(8) For devices without the ADC12, the parametric with ADC12SR = 0 are applicable.

Table 5-32 12-Bit DAC, Supply Specifications

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC = DVCC, AVSS = DVSS = 0 V 2.20 3.60 V
IDD Supply current, single DAC channel(1)(2) DAC12AMPx = 2, DAC12IR = 0, DAC12IOG = 1
DAC12_xDAT  =  0800h
VeREF+  =  VREF+  = 1.5 V		 3 V 65 110 µA
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT  =  0800h,
VeREF+ =  VREF+  =  AVCC 		2.2 V, 3 V 65 110
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT  =  0800h,
VeREF+  =  VREF+  =  AVCC 		250 300
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT  =  0800h,
VeREF+  =  VREF+  =  AVCC 		750 1000
PSRR Power supply rejection ratio(3)(4) DAC12_xDAT = 800h, VeREF+ = 1.5 V,
ΔAVCC  =  100 mV		 2.2 V 70 dB
DAC12_xDAT = 800h, VeREF+ = 1.5 V or 2.5 V,
ΔAVCC  =  100 mV		 3 V 70
(1) No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
(2) Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Table 5-35.
(3) PSRR = 20 log (ΔAVCC / ΔVDAC12_xOUT)
(4) The internal reference is not used.

Table 5-33 12-Bit DAC, Linearity Specifications

See Figure 5-17, over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Resolution 12-bit monotonic 12 bits
INL Integral nonlinearity(1) VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 2.2 V ±2 ±4 LSB
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 3 V ±2 ±4
DNL Differential nonlinearity(1) VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 2.2 V ±0.4 ±1 LSB
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 3 V ±0.4 ±1
EO Offset voltage Without calibration(1) (2) VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1		 2.2 V ±21 mV
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1		 3 V ±21
With calibration(1) (2) VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1		 2.2 V ±1.5
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1		 3 V ±1.5
dE(O)/dT Offset error temperature coefficient(1) With calibration 2.2 V, 3 V ±10 µV/°C
EG Gain error VeREF+ = 1.5 V 2.2 V ±2.5 %FSR
VeREF+ = 2.5 V 3 V ±2.5
dE(G)/dT Gain temperature coefficient(1) 2.2 V, 3 V 10 ppm of FSR/°C
tOffset_Cal Time for offset calibration(3) DAC12AMPx = 2 2.2 V, 3 V 165 ms
DAC12AMPx = 3, 5 66
DAC12AMPx = 4, 6, 7 16.5
(1) Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and “b” of the first-order equation: y = a + bx. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
(2) The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON.
(3) The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx = {0, 1}. TI recommends configuring the DAC12 module before initiating calibration. Port activity during calibration may affect accuracy and is not recommended.
MSP430F6459-HIREL slau208dac12a-101.gif Figure 5-17 Linearity Test Load Conditions and Gain/Offset Definition

Table 5-34 12-Bit DAC, Output Specifications

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VO Output voltage range(1) (see Figure 5-18) No load, VeREF+ = AVCC, DAC12_xDAT  =  0h,
DAC12IR  =  1, DAC12AMPx  =  7		 2.2 V, 3 V 0 0.005 V
No load, VeREF+ = AVCC,
DAC12_xDAT  =  0FFFh, DAC12IR  =  1,
DAC12AMPx  =  7		 AVCC – 0.05 AVCC
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT  =  0h, DAC12IR  =  1,
DAC12AMPx  =  7		 0 0.1
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT  =  0FFFh, DAC12IR  =  1,
DAC12AMPx  =  7		 AVCC – 0.13 AVCC
CL(DAC12) Maximum DAC12 load capacitance 2.2 V, 3 V 100 pF
IL(DAC12) Maximum DAC12 load current DAC12AMPx = 2, DAC12_xDAT = 0FFFh,
VO/P(DAC12) > AVCC – 0.3		 2.2 V, 3 V –1 mA
DAC12AMPx = 2, DAC12_xDAT = 0h,
VO/P(DAC12) < 0.3 V		 1
RO/P(DAC12) Output resistance (see Figure 5-18) RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h		 2.2 V, 3 V 150 250 Ω
RLoad = 3 kΩ, VO/P(DAC12) > AVCC – 0.3 V,
DAC12_xDAT = 0FFFh		 150 250
RLoad = 3 kΩ,
0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V		 6
(1) Data is valid after the offset calibration of the output amplifier.
MSP430F6459-HIREL slau208dac12a-102.gif Figure 5-18 DAC12_x Output Resistance Tests

Table 5-35 12-Bit DAC, Reference Input Specifications

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VeREF+ Reference input voltage range DAC12IR = 0(1) (2) 2.2 V, 3 V AVCC/3 AVCC + 0.2 V
DAC12IR = 1(3) (4) AVCC AVCC + 0.2
Ri(VREF+), Ri(VeREF+) Reference input resistance DAC12_0 IR = DAC12_1 IR = 0 2.2 V, 3 V 20 MΩ
DAC12_0 IR = 1, DAC12_1 IR = 0 52 kΩ
DAC12_0 IR = 0, DAC12_1 IR = 1 52
DAC12_0 IR = DAC12_1 IR = 1,
DAC12_0 SREFx = DAC12_1 SREFx(5) 		26
(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
(2) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
(4) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
(5) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel reducing the reference input resistance.

Table 5-36 12-Bit DAC, Dynamic Specifications

VREF = VCC, DAC12IR = 1 (see Figure 5-19 and Figure 5-20), over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
tON DAC12 on time DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB(1) (see Figure 5-19)		 DAC12AMPx = 0 → {2, 3, 4} 2.2 V, 3 V 60 120 µs
DAC12AMPx = 0 → {5, 6} 15 30
DAC12AMPx = 0 → 7 6 12
tS(FS) Settling time, full scale DAC12_xDAT =
80h → F7Fh → 80h		 DAC12AMPx = 2 2.2 V, 3 V 100 200 µs
DAC12AMPx = 3, 5 40 80
DAC12AMPx = 4, 6, 7 15 30
tS(C-C) Settling time, code to code DAC12_xDAT =
3F8h → 408h → 3F8h,
BF8h → C08h → BF8h		 DAC12AMPx = 2 2.2 V, 3 V 5 µs
DAC12AMPx = 3, 5 2
DAC12AMPx = 4, 6, 7 1
SR Slew rate DAC12_xDAT =
80h → F7Fh → 80h(2) 		DAC12AMPx = 2 2.2 V, 3 V 0.05 0.35 V/µs
DAC12AMPx = 3, 5 0.35 1.10
DAC12AMPx = 4, 6, 7 1.50 5.20
Glitch energy DAC12_xDAT =
800h → 7FFh → 800h		 DAC12AMPx = 7 2.2 V, 3 V 35 nV-s
(1) RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 5-19.
(2) Slew rate applies to output voltage steps ≥ 200 mV.
MSP430F6459-HIREL slau208dac12a-103.gif Figure 5-19 Settling Time and Glitch Energy Testing
MSP430F6459-HIREL slau208dac12a-104.gif Figure 5-20 Slew Rate Testing

Table 5-37 12-Bit DAC, Dynamic Specifications (Continued)

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
BW–3dB 3-dB bandwidth,
VDC = 1.5 V,
VAC = 0.1 VPP (see Figure 5-21)		 DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
TJ = 25°C		 2.2 V, 3 V 40 kHz
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
TJ = 25°C		 180
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
TJ = 25°C		 550
Channel-to-channel crosstalk(1) (see Figure 5-22) DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
fDAC12_1OUT = 10 kHz at 50/50 duty cycle,
TJ = 25°C		 2.2 V, 3 V –80 dB
DAC12_0DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No load,
fDAC12_0OUT = 10 kHz at 50/50 duty cycle,
TJ = 25°C		 –80
(1) RLoad = 3 kΩ, CLoad = 100 pF
MSP430F6459-HIREL slau208dac12a-105.gif Figure 5-21 Test Conditions for 3-dB Bandwidth Specification
MSP430F6459-HIREL slau208dac12a-106.gif Figure 5-22 Crosstalk Test Conditions

Table 5-38 Comparator_B

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC Supply voltage 1.8 3.6 V
IAVCC_COMP Comparator operating supply current into AVCC terminal, Excludes reference resistor ladder CBPWRMD = 00 1.8 V 40 µA
2.2 V 30 50
3 V 40 65
CBPWRMD = 01 2.2 V, 3 V 10 30
CBPWRMD = 10 2.2 V, 3 V 0.1 0.5
IAVCC_REF Quiescent current of local reference voltage amplifier into AVCC terminal CBREFACC = 1,
CBREFLx = 01		 22 µA
VIC Common mode input range 0 VCC – 1 V
VOFFSET Input offset voltage CBPWRMD = 00 ±20 mV
CBPWRMD = 01, 10 ±10
CIN Input capacitance 5 pF
RSIN Series input resistance ON, switch closed 3 4 kΩ
OFF, switch opened 50 MΩ
tPD Propagation delay, response time CBPWRMD = 00, CBF = 0 450 ns
CBPWRMD = 01, CBF = 0 600
CBPWRMD = 10, CBF = 0 50 µs
tPD,filter Propagation delay with filter active CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 00		 0.35 0.6 1.0 µs
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 01		 0.6 1.0 1.8
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 10		 1.0 1.8 3.4
CBPWRMD = 00, CBON = 1,
CBF = 1, CBFDLY = 11		 1.8 3.4 6.5
tEN_CMP Comparator enable time, settling time CBON = 0 to CBON = 1
CBPWRMD = 00, 01, 10		 1 2 µs
tEN_REF Resistor reference enable time CBON = 0 to CBON = 1 0.3 1.5 µs
VCB_REF Reference voltage for a given tap VIN = reference into resistor ladder, n = 0 to 31 VIN × (n + 0.5) / 32 VIN × (n + 1) / 32 VIN × (n + 1.5) / 32 V

Table 5-39 Flash Memory

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DVCC(PGM/ERASE) Program and erase supply voltage 1.8 3.6 V
IPGM Average supply current from DVCC during program 3 5 mA
IERASE Average supply current from DVCC during erase 6 17 mA
IMERASE, IBANK Average supply current from DVCC during mass erase or bank erase 6 17 mA
tCPT Cumulative program time See (1) 16 ms
Program and erase endurance 103 105 cycles
tRetention Data retention duration TJ = 25°C 100 years
tWord Word or byte program time See (2) 64 85 µs
tBlock, 0 Block program time for first byte or word See (2) 49 65 µs
tBlock, 1–(N–1) Block program time for each additional byte or word, except for last byte or word See (2) 37 49 µs
tBlock, N Block program time for last byte or word See (2) 55 73 µs
tSeg Erase Erase time for segment, mass erase, and bank erase when available See (2) 23 32 ms
fMCLK,MRG MCLK frequency in marginal read mode
(FCTL4.MRG0 = 1 or FCTL4.MRG1 = 1)		 0 1 MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming methods: individual word write, individual byte write, and block write modes.
(2) These values are hardwired into the state machine of the flash controller.

5.14.4 Emulation and Debug

Table 5-40 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz
tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 0.025 15 µs
tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1) 2.2 V, 3 V 1 µs
tSBW,Rst Spy-Bi-Wire return to normal operation time 15 100 µs
fTCK TCK input frequency for 4-wire JTAG(2) 2.2 V 0 5 MHz
3 V 0 10
Rinternal Internal pulldown resistance on TEST 2.2 V, 3 V 45 60 80 kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.