JAJSGB6A February   2015  – October 2018 MSP430F6720A , MSP430F6721A , MSP430F6723A , MSP430F6724A , MSP430F6725A , MSP430F6726A , MSP430F6730A , MSP430F6731A , MSP430F6733A , MSP430F6734A , MSP430F6735A , MSP430F6736A

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-5 Signal Descriptions, PZ Package
      2. Table 4-6 Signal Descriptions, PN Package
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7 Thermal Resistance Characteristics
    8. 5.8 Timing and Switching Characteristics
      1. 5.8.1  Power Supply Sequencing
      2. 5.8.2  Reset Timing
        1. Table 5-1 Wake-up Times From Low-Power Modes and Reset
      3. 5.8.3  Clock Specifications
        1. Table 5-2 Crystal Oscillator, XT1, Low-Frequency Mode
        2. Table 5-3 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        3. Table 5-4 Internal Reference, Low-Frequency Oscillator (REFO)
        4. Table 5-5 DCO Frequency
      4. 5.8.4  Digital I/O Ports
        1. Table 5-6  Schmitt-Trigger Inputs, General-Purpose I/O
        2. Table 5-7  Inputs, Ports P1 and P2
        3. Table 5-8  Leakage Current, General-Purpose I/O
        4. Table 5-9  Outputs, General-Purpose I/O (Full Drive Strength)
        5. 5.8.4.1    Typical Characteristics, General-Purpose I/O (Full Drive Strength)
        6. Table 5-10 Outputs, General-Purpose I/O (Reduced Drive Strength)
        7. 5.8.4.2    Typical Characteristics, General-Purpose I/O (Reduced Drive Strength)
        8. Table 5-11 Output Frequency, General-Purpose I/O
      5. 5.8.5  Power-Management Module (PMM)
        1. Table 5-12 PMM, Brownout Reset (BOR)
        2. Table 5-13 PMM, Core Voltage
        3. Table 5-14 PMM, SVS High Side
        4. Table 5-15 PMM, SVM High Side
        5. Table 5-16 PMM, SVS Low Side
        6. Table 5-17 PMM, SVM Low Side
      6. 5.8.6  Auxiliary Supplies Module
        1. Table 5-18 Auxiliary Supplies, Recommended Operating Conditions
        2. Table 5-19 Auxiliary Supplies, AUX3 (Backup Subsystem) Currents
        3. Table 5-20 Auxiliary Supplies, Auxiliary Supply Monitor
        4. Table 5-21 Auxiliary Supplies, Switch ON-Resistance
        5. Table 5-22 Auxiliary Supplies, Switching Time
        6. Table 5-23 Auxiliary Supplies, Switch Leakage
        7. Table 5-24 Auxiliary Supplies, Auxiliary Supplies to ADC10_A
        8. Table 5-25 Auxiliary Supplies, Charge-Limiting Resistor
      7. 5.8.7  Timer_A Module
        1. Table 5-26 Timer_A
      8. 5.8.8  eUSCI Module
        1. Table 5-27 eUSCI (UART Mode) Clock Frequency
        2. Table 5-28 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-29 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-30 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-31 eUSCI (SPI Slave Mode)
        6. Table 5-32 eUSCI (I2C Mode)
      9. 5.8.9  LCD Controller
        1. Table 5-33 LCD_C Operating Conditions
        2. Table 5-34 LCD_C Electrical Characteristics
      10. 5.8.10 SD24_B Module
        1. Table 5-35 SD24_B Power Supply and Recommended Operating Conditions
        2. Table 5-36 SD24_B Analog Input
        3. Table 5-37 SD24_B Supply Currents
        4. Table 5-38 SD24_B Performance
        5. Table 5-39 SD24_B AC Performance
        6. Table 5-40 SD24_B AC Performance
        7. Table 5-41 SD24_B AC Performance
        8. Table 5-42 SD24_B External Reference Input
      11. 5.8.11 ADC10_A Module
        1. Table 5-43 10-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-44 10-Bit ADC, Timing Parameters
        3. Table 5-45 10-Bit ADC, Linearity Parameters
        4. Table 5-46 10-Bit ADC, External Reference
      12. 5.8.12 REF Module
        1. Table 5-47 REF, Built-In Reference
      13. 5.8.13 Flash
        1. Table 5-48 Flash Memory
      14. 5.8.14 Emulation and Debug
        1. Table 5-49 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Instruction Set
    4. 6.4  Operating Modes
    5. 6.5  Interrupt Vector Addresses
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  Flash Memory
    9. 6.9  RAM
    10. 6.10 Backup RAM
    11. 6.11 Peripherals
      1. 6.11.1  Oscillator and System Clock
      2. 6.11.2  Power-Management Module (PMM)
      3. 6.11.3  Auxiliary Supply System
      4. 6.11.4  Backup Subsystem
      5. 6.11.5  Digital I/O
      6. 6.11.6  Port Mapping Controller
      7. 6.11.7  System Module (SYS)
      8. 6.11.8  Watchdog Timer (WDT_A)
      9. 6.11.9  DMA Controller
      10. 6.11.10 CRC16
      11. 6.11.11 Hardware Multiplier
      12. 6.11.12 Enhanced Universal Serial Communication Interface (eUSCI)
      13. 6.11.13 ADC10_A
      14. 6.11.14 SD24_B
      15. 6.11.15 TA0
      16. 6.11.16 TA1
      17. 6.11.17 TA2
      18. 6.11.18 TA3
      19. 6.11.19 SD24_B Triggers
      20. 6.11.20 ADC10_A Triggers
      21. 6.11.21 Real-Time Clock (RTC_C)
      22. 6.11.22 Reference (REF) ModuleVoltage Reference
      23. 6.11.23 LCD_C
      24. 6.11.24 Embedded Emulation Module (EEM) (S Version)
    12. 6.12 Input/Output Diagrams
      1. 6.12.1  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ and MSP430F67xxAIPN)
      2. 6.12.2  Port P1 (P1.2) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ and MSP430F67xxAIPN)
      3. 6.12.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ and MSP430F67xxAIPN)
      4. 6.12.4  Port P1 (P1.6 and P1.7) (MSP430F67xxAIPZ and MSP430F67xxAIPN) and Port P2 (P2.0 and P2.1) (MSP430F67xxAIPZ Only) Input/Output With Schmitt Trigger
      5. 6.12.5  Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      6. 6.12.6  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      7. 6.12.7  Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      8. 6.12.8  Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      9. 6.12.9  Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      10. 6.12.10 Port P9 (P9.0) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      11. 6.12.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (MSP430F67xxAIPZ Only)
      12. 6.12.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
      13. 6.12.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
      14. 6.12.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
      15. 6.12.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (MSP430F67xxAIPN Only)
      16. 6.12.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      17. 6.12.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    13. 6.13 Device Descriptors (TLV)
    14. 6.14 Memory
      1. 6.14.1 Memory Organization
      2. 6.14.2 Peripheral File Map
    15. 6.15 Identification
      1. 6.15.1 Revision Identification
      2. 6.15.2 Device Identification
      3. 6.15.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1  使い始めと次の手順
    2. 8.2  Device Nomenclature
    3. 8.3  ツールとソフトウェア
    4. 8.4  ドキュメントのサポート
    5. 8.5  関連リンク
    6. 8.6  Community Resources
    7. 8.7  商標
    8. 8.8  静電気放電に関する注意事項
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.3 Signal Descriptions

Table 4-5 describes the signals for all device variants in the PZ package. See Table 4-6 for signal descriptions in the PN package.

Table 4-5 Signal Descriptions, PZ Package

FUNCTION SIGNAL NAME PIN NO. SIGNAL TYPE DESCRIPTION
ADC10 A0 16 I Analog input A0 for 10-bit ADC
A1 15 I Analog input A1 for 10-bit ADC
A2 14 I Analog input A2 for 10-bit ADC
A3 13 I Analog input A3 for 10-bit ADC
A4 12 I Analog input A4 for 10-bit ADC
A5 11 I Analog input A5 for 10-bit ADC
ADC10CLK 98 O ADC10_A clock output
VeREF+ 15 I Positive terminal for the ADC reference voltage for an external applied reference voltage
VeREF- 14 I Negative terminal for the ADC reference voltage for an external applied reference voltage
BSL BSL_RX 50 I Bootloader data receive
BSL_TX 49 O Bootloader data transmit
Clock ACLK 99 O ACLK clock output
MCLK 97 O MCLK clock output
PM_RTCCLK 51 O Default mapping: RTCCLK clock output
RTCCLK 42 O RTCCLK clock output
SMCLK 96 O SMCLK clock output
XIN 24 I Input terminal for crystal oscillator
XOUT 25 O Output terminal for crystal oscillator
Debug SBWTCK 95 I Spy-Bi-Wire input clock
SBWTDIO 100 I/O Spy-Bi-Wire data input/output
TCK 99 I Test clock
TCLK 97 I Test clock input
TDI 97 I Test data input
TDO 96 O Test data output
TEST 95 I Test mode pin – select digital I/O on JTAG pins
TMS 98 I Test mode select
GPIO P1.0 14 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.1 15 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.2 16 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.3 17 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.4 27 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.5 28 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.6 36 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.7 37 I/O General-purpose digital I/O with port interrupt and mappable secondary function
GPIO P2.0 38 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.1 39 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.2 43 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.3 44 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.4 45 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.5 46 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.6 47 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.7 48 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P3.0 49 I/O General-purpose digital I/O with mappable secondary function
P3.1 50 I/O General-purpose digital I/O with mappable secondary function
P3.2 51 I/O General-purpose digital I/O with mappable secondary function
P3.3 52 I/O General-purpose digital I/O with mappable secondary function
P3.4 53 I/O General-purpose digital I/O with mappable secondary function
P3.5 54 I/O General-purpose digital I/O with mappable secondary function
P3.6 55 I/O General-purpose digital I/O with mappable secondary function
P3.7 56 I/O General-purpose digital I/O with mappable secondary function
P4.0 57 I/O General-purpose digital I/O
P4.1 58 I/O General-purpose digital I/O
P4.2 59 I/O General-purpose digital I/O
P4.3 60 I/O General-purpose digital I/O
P4.4 61 I/O General-purpose digital I/O
P4.5 62 I/O General-purpose digital I/O
P4.6 63 I/O General-purpose digital I/O
P4.7 64 I/O General-purpose digital I/O
P5.0 65 I/O General-purpose digital I/O
P5.1 66 I/O General-purpose digital I/O
P5.2 67 I/O General-purpose digital I/O
P5.3 68 I/O General-purpose digital I/O
P5.4 69 I/O General-purpose digital I/O
P5.5 70 I/O General-purpose digital I/O
P5.6 71 I/O General-purpose digital I/O
P5.7 72 I/O General-purpose digital I/O
P6.0 73 I/O General-purpose digital I/O
P6.1 76 I/O General-purpose digital I/O
P6.2 77 I/O General-purpose digital I/O
P6.3 78 I/O General-purpose digital I/O
P6.4 79 I/O General-purpose digital I/O
P6.5 80 I/O General-purpose digital I/O
P6.6 81 I/O General-purpose digital I/O
P6.7 82 I/O General-purpose digital I/O
GPIO P7.0 83 I/O General-purpose digital I/O
P7.1 84 I/O General-purpose digital I/O
P7.2 85 I/O General-purpose digital I/O
P7.3 86 I/O General-purpose digital I/O
P7.4 87 I/O General-purpose digital I/O
P7.5 88 I/O General-purpose digital I/O
P7.6 89 I/O General-purpose digital I/O
P7.7 90 I/O General-purpose digital I/O
P8.0 91 I/O General-purpose digital I/O
P8.1 92 I/O General-purpose digital I/O
P8.2 93 I/O General-purpose digital I/O
P8.3 94 I/O General-purpose digital I/O
P8.4 30 I/O General-purpose digital I/O
P8.5 31 I/O General-purpose digital I/O
P8.6 40 I/O General-purpose digital I/O
P8.7 41 I/O General-purpose digital I/O
P9.0 42 I/O General-purpose digital I/O
P9.1 11 I/O General-purpose digital I/O
P9.2 12 I/O General-purpose digital I/O
P9.3 13 I/O General-purpose digital I/O
PJ.0 96 I/O General-purpose digital I/O
PJ.1 97 I/O General-purpose digital I/O
PJ.2 98 I/O General-purpose digital I/O
PJ.3 99 I/O General-purpose digital I/O
I2C PM_UCB0SCL 38 I/O Default mapping: eUSCI_B0 I2C clock
PM_UCB0SDA 39 I/O Default mapping: eUSCI_B0 I2C data
LCD COM0 32 O LCD common output COM0 for LCD backplane
COM1 33 O LCD common output COM1 for LCD backplane
COM2 34 O LCD common output COM2 for LCD backplane
COM3 35 O LCD common output COM3 for LCD backplane
COM4 36 O LCD common output COM4 for LCD backplane
COM5 37 O LCD common output COM5 for LCD backplane
COM6 38 O LCD common output COM6 for LCD backplane
COM7 39 O LCD common output COM7 for LCD backplane
LCDCAP 29 I/O LCD capacitor connection
CAUTION: This pin must be connected to DVSS if not used.
LCDREF 27 I External reference voltage input for regulated LCD voltage
R03 17 I/O Input/output port of lowest analog LCD voltage (V5)
R13 27 I/O Input/output port of third most positive analog LCD voltage (V3 or V4)
R23 28 I/O Input/output port of second most positive analog LCD voltage (V2)
R33 29 I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.
LCD S0 94 O LCD segment output S0
S1 93 O LCD segment output S1
S2 92 O LCD segment output S2
S3 91 O LCD segment output S3
S4 90 O LCD segment output S4
S5 89 O LCD segment output S5
S6 88 O LCD segment output S6
S7 87 O LCD segment output S7
S8 86 O LCD segment output S8
S9 85 O LCD segment output S9
S10 84 O LCD segment output S10
S11 83 O LCD segment output S11
S12 82 O LCD segment output S12
S13 81 O LCD segment output S13
S14 80 O LCD segment output S14
S15 79 O LCD segment output S15
S16 78 O LCD segment output S16
S17 77 O LCD segment output S17
S18 76 O LCD segment output S18
S19 73 O LCD segment output S19
S20 72 O LCD segment output S20
S21 71 O LCD segment output S21
S22 70 O LCD segment output S22
S23 69 O LCD segment output S23
S24 68 O LCD segment output S24
S25 67 O LCD segment output S25
S26 66 O LCD segment output S26
S27 65 O LCD segment output S27
S28 64 O LCD segment output S28
S29 63 O LCD segment output S29
S30 62 O LCD segment output S30
S31 61 O LCD segment output S31
S32 60 O LCD segment output S32
S33 59 O LCD segment output S33
S34 58 O LCD segment output S34
S35 57 O LCD segment output S35
S36 56 O LCD segment output S36
S37 55 O LCD segment output S37
S38 54 O LCD segment output S38
S39 53 O LCD segment output S39
Power AUXVCC1 19 P Auxiliary power supply AUXVCC1
AUXVCC2 18 P Auxiliary power supply AUXVCC2
AUXVCC3 26 P Auxiliary power supply AUXVCC3 for back up subsystem
AVCC 9 P Analog power supply
AVSS 8 P Analog ground supply
DVCC 21 P Digital power supply
DVSS 22
75		 P Digital ground supply
DVSYS(3) 74 P Digital power supply for I/Os
VASYS 10 P Analog power supply selected among AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS (see Table 5-18).
VCORE(1) 23 P Regulated core power supply (internal use only, no external current loading)
VDSYS(3) 20 P Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS (see Table 5-18).
SD24 PM_SD0DIO 54 I/O Default mapping: SD24_B converter 0 bit stream data input/output
PM_SD1DIO 55 I/O Default mapping: SD24_B converter 1 bit stream data input/output
PM_SD2DIO 56 I/O Default mapping: SD24_B converter 2 bit stream data input/output (not available on F672xA devices)
PM_SDCLK 53 I/O Default mapping: SD24_B bit stream clock input/output
SD0N0 2 I SD24_B negative analog input for converter 0(2)
SD0P0 1 I SD24_B positive analog input for converter 0(2)
SD1N0 4 I SD24_B negative analog input for converter 1(2)
SD1P0 3 I SD24_B positive analog input for converter 1(2)
SD2N0 6 I SD24_B negative analog input for converter 2(2) (not available on F672xA devices)
SD2P0 5 I SD24_B positive analog input for converter 2(2) (not available on F672xA devices)
VREF 7 O SD24_B external reference voltage
SPI PM_UCA0CLK 36 I/O Default mapping: eUSCI_A0 clock input/output
PM_UCA0SIMO 17 I/O Default mapping: eUSCI_A0 SPI slave in/master out
PM_UCA0SOMI 16 I/O Default mapping: eUSCI_A0 SPI slave out/master in
PM_UCA1CLK 45 I/O Default mapping: eUSCI_A1 clock input/output
PM_UCA1SIMO 28 I/O Default mapping: eUSCI_A1 SPI slave in/master out
PM_UCA1SOMI 27 I/O Default mapping: eUSCI_A1 SPI slave out/master in
PM_UCA2CLK 46 I/O Default mapping: eUSCI_A2 clock input/output
PM_UCA2SIMO 44 I/O Default mapping: eUSCI_A2 SPI slave in/master out
PM_UCA2SOMI 43 I/O Default mapping: eUSCI_A2 SPI slave out/master in
PM_UCB0CLK 37 I/O Default mapping: eUSCI_B0 clock input/output
PM_UCB0SIMO 39 I/O Default mapping: eUSCI_B0 SPI slave in/master out
PM_UCB0SOMI 38 I/O Default mapping: eUSCI_B0 SPI slave out/master in
System NMI 100 I Nonmaskable interrupt input
RST 100 I Reset input active low(4)
Timer_A PM_TA0.0 14 I/O Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
PM_TA0.1 15 I/O Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
PM_TA0.2 52 I/O Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
PM_TA1.0 47 I/O Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
PM_TA1.1 48 I/O Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
PM_TA2.0 49 I/O Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
PM_TA2.1 50 I/O Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
PM_TACLK 51 I Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3
TA1.0 30 I/O Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output
TA1.1 31 I/O Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output
TA2.0 40 I/O Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output
TA2.1 41 I/O Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output
TACLK 42 I Timer clock input TACLK for TA0, TA1, TA2, TA3
UART PM_UCA0RXD 16 I Default mapping: eUSCI_A0 UART receive data
PM_UCA0TXD 17 O Default mapping: eUSCI_A0 UART transmit data
PM_UCA1RXD 27 I Default mapping: eUSCI_A1 UART receive data
PM_UCA1TXD 28 O Default mapping: eUSCI_A1 UART transmit data
PM_UCA2RXD 43 I Default mapping: eUSCI_A2 UART receive data
PM_UCA2TXD 44 O Default mapping: eUSCI_A2 UART transmit data
(1) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE.
(2) TI recommends shorting unused analog input pairs and connect them to analog ground.
(3) The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
(4) When this pin is configured as reset, the internal pullup resistor is enabled by default.

Table 4-6 describes the signals for all device variants in the PN package. See Table 4-5 for signal descriptions in the PZ package.

Table 4-6 Signal Descriptions, PN Package

FUNCTION SIGNAL NAME PIN NO. SIGNAL TYPE(1) DESCRIPTION
ADC10 A0 13 I Analog input A0 for 10-bit ADC
A1 12 I Analog input A1 for 10-bit ADC
A2 11 I Analog input A2 for 10-bit ADC
ADC10CLK 78 O ADC10_A clock output
VeREF+ 12 I Positive terminal for the ADC reference voltage for an external applied reference voltage
VeREF- 11 I Negative terminal for the ADC reference voltage for an external applied reference voltage
BSL BSL_RX 42 I Bootloader data receive
BSL_TX 41 O Bootloader data transmit
Clock ACLK 79 O ACLK clock output
MCLK 77 O MCLK clock output
PM_RTCCLK 43 O Default mapping: RTCCLK clock output
SMCLK 76 O SMCLK clock output
XIN 21 I Input terminal for crystal oscillator
XOUT 22 O Output terminal for crystal oscillator
Debug SBWTCK 75 I Spy-Bi-Wire input clock
SBWTDIO 80 I/O Spy-Bi-Wire data input/output
TCK 79 I Test clock
TCLK 77 I Test clock input
TDI 77 I Test data input
TDO 76 O Test data output
TEST 75 I Test mode pin – select digital I/O on JTAG pins
TMS 78 I Test mode select
GPIO P1.0 11 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.1 12 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.2 13 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.3 14 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.4 24 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.5 25 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.6 31 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P1.7 32 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.0 33 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.1 34 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.2 35 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.3 36 I/O General-purpose digital I/O with port interrupt and mappable secondary function
GPIO P2.4 37 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.5 38 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.6 39 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.7 40 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P3.0 41 I/O General-purpose digital I/O with mappable secondary function
P3.1 42 I/O General-purpose digital I/O with mappable secondary function
P3.2 43 I/O General-purpose digital I/O with mappable secondary function
P3.3 44 I/O General-purpose digital I/O with mappable secondary function
P3.4 45 I/O General-purpose digital I/O with mappable secondary function
P3.5 46 I/O General-purpose digital I/O with mappable secondary function
P3.6 47 I/O General-purpose digital I/O with mappable secondary function
P3.7 48 I/O General-purpose digital I/O with mappable secondary function
P4.0 49 I/O General-purpose digital I/O
P4.1 50 I/O General-purpose digital I/O
P4.2 51 I/O General-purpose digital I/O
P4.3 52 I/O General-purpose digital I/O
P4.4 53 I/O General-purpose digital I/O
P4.5 54 I/O General-purpose digital I/O
P4.6 55 I/O General-purpose digital I/O
P4.7 56 I/O General-purpose digital I/O
P5.0 57 I/O General-purpose digital I/O
P5.1 58 I/O General-purpose digital I/O
P5.2 61 I/O General-purpose digital I/O
P5.3 62 I/O General-purpose digital I/O
P5.4 63 I/O General-purpose digital I/O
P5.5 64 I/O General-purpose digital I/O
P5.6 65 I/O General-purpose digital I/O
P5.7 66 I/O General-purpose digital I/O
P6.0 67 I/O General-purpose digital I/O
P6.1 68 I/O General-purpose digital I/O
P6.2 69 I/O General-purpose digital I/O
P6.3 70 I/O General-purpose digital I/O
P6.4 71 I/O General-purpose digital I/O
P6.5 72 I/O General-purpose digital I/O
P6.6 73 I/O General-purpose digital I/O
P6.7 74 I/O General-purpose digital I/O
PJ.0 76 I/O General-purpose digital I/O
PJ.1 77 I/O General-purpose digital I/O
PJ.2 78 I/O General-purpose digital I/O
PJ.3 79 I/O General-purpose digital I/O
I2C PM_UCB0SCL 33 I/O Default mapping: eUSCI_B0 I2C clock
PM_UCB0SDA 34 I/O Default mapping: eUSCI_B0 I2C data
LCD COM0 27 O LCD common output COM0 for LCD backplane
COM1 28 O LCD common output COM1 for LCD backplane
COM2 29 O LCD common output COM2 for LCD backplane
COM3 30 O LCD common output COM3 for LCD backplane
COM4 31 O LCD common output COM4 for LCD backplane
COM5 32 O LCD common output COM5 for LCD backplane
COM6 33 O LCD common output COM6 for LCD backplane
COM7 34 O LCD common output COM7 for LCD backplane
LCDCAP 26 I/O LCD capacitor connection
CAUTION: This pin must be connected to DVSS if not used.
LCDREF 24 I External reference voltage input for regulated LCD voltage
R03 14 I/O Input/output port of lowest analog LCD voltage (V5)
R13 24 I/O Input/output port of third most positive analog LCD voltage (V3 or V4)
R23 25 I/O Input/output port of second most positive analog LCD voltage (V2)
R33 26 I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: This pin must be connected to DVSS if not used.
S0 74 O LCD segment output S0
S1 73 O LCD segment output S1
S2 72 O LCD segment output S2
S3 71 O LCD segment output S3
S4 70 O LCD segment output S4
S5 69 O LCD segment output S5
S6 68 O LCD segment output S6
S7 67 O LCD segment output S7
S8 66 O LCD segment output S8
S9 65 O LCD segment output S9
S10 64 O LCD segment output S10
S11 63 O LCD segment output S11
S12 62 O LCD segment output S12
S13 61 O LCD segment output S13
S14 58 O LCD segment output S14
S15 57 O LCD segment output S15
S16 56 O LCD segment output S16
S17 55 O LCD segment output S17
S18 54 O LCD segment output S18
S19 53 O LCD segment output S19
S20 52 O LCD segment output S20
S21 51 O LCD segment output S21
S22 50 O LCD segment output S22
S23 49 O LCD segment output S23
S24 48 O LCD segment output S24
S25 47 O LCD segment output S25
S26 46 O LCD segment output S26
LCD S27 45 O LCD segment output S27
S28 44 O LCD segment output S28
S29 43 O LCD segment output S29
S30 42 O LCD segment output S30
S31 41 O LCD segment output S31
S32 40 O LCD segment output S32
S33 39 O LCD segment output S33
S34 38 O LCD segment output S34
S35 37 O LCD segment output S35
S36 36 O LCD segment output S36
S37 35 O LCD segment output S37
S38 34 O LCD segment output S38
S39 33 O LCD segment output S39
Power AUXVCC1 16 P Auxiliary power supply AUXVCC1
AUXVCC2 15 P Auxiliary power supply AUXVCC2
AUXVCC3 23 P Auxiliary power supply AUXVCC3 for backup subsystem
AVCC 9 P Analog power supply
AVSS 8 P Analog ground supply
DVCC 18 P Digital power supply
DVSS 19 P Digital ground supply
DVSS 60 P Digital ground supply
DVSYS(4) 59 P Digital power supply for I/Os
VASYS 10 P Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS (see Table 5-18).
VCORE(2) 20 P Regulated core power supply (internal use only, no external current loading)
VDSYS(4) 17 P Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS (see Table 5-18).
SD24 PM_SD0DIO 46 I/O Default mapping: SD24_B converter 0 bit stream data input/output
PM_SD1DIO 47 I/O Default mapping: SD24_B converter 1 bit stream data input/output
PM_SD2DIO 48 I/O Default mapping: SD24_B converter 2 bit stream data input/output (not available on F672xA devices)
PM_SDCLK 45 I/O Default mapping: SD24_B bit stream clock input/output
SD0N0 2 I SD24_B negative analog input for converter 0(3)
SD0P0 1 I SD24_B positive analog input for converter 0(3)
SD1N0 4 I SD24_B negative analog input for converter 1(3)
SD1P0 3 I SD24_B positive analog input for converter 1(3)
SD2N0 6 I SD24_B negative analog input for converter 2(3) (not available on F672xA devices)
SD2P0 5 I SD24_B positive analog input for converter 2(3) (not available on F672xA devices)
VREF 7 I SD24_B external reference voltage
SPI PM_UCA0CLK 31 I/O Default mapping: eUSCI_A0 clock input/output
PM_UCA0SIMO 14 I/O Default mapping: eUSCI_A0 SPI slave in/master out
PM_UCA0SOMI 13 I/O Default mapping: eUSCI_A0 SPI slave out/master in
PM_UCA1CLK 37 I/O Default mapping: eUSCI_A1 clock input/output
PM_UCA1SIMO 25 I/O Default mapping: eUSCI_A1 SPI slave in/master out
PM_UCA1SOMI 24 I/O Default mapping: eUSCI_A1 SPI slave out/master in
PM_UCA2CLK 38 I/O Default mapping: eUSCI_A2 clock input/output
PM_UCA2SIMO 36 I/O Default mapping: eUSCI_A2 SPI slave in/master out
PM_UCA2SOMI 35 I/O Default mapping: eUSCI_A2 SPI slave out/master in
PM_UCB0CLK 32 I/O Default mapping: eUSCI_B0 clock input/output
PM_UCB0SIMO 34 I/O Default mapping: eUSCI_B0 SPI slave in/master out
PM_UCB0SOMI 33 I/O Default mapping: eUSCI_B0 SPI slave out/master in
System NMI 80 I Nonmaskable interrupt input
RST 80 I/O Reset input active low(5)
Timer_A PM_TA0.0 11 I/O Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
PM_TA0.1 12 I/O Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
PM_TA0.2 44 I/O Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
PM_TA1.0 39 I/O Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
PM_TA1.1 40 I/O Default mapping: Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
PM_TA2.0 41 I/O Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
PM_TA2.1 42 I/O Default mapping: Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
PM_TACLK 43 I Default mapping: Timer clock input TACLK for TA0, TA1, TA2, TA3
UART PM_UCA0RXD 13 I Default mapping: eUSCI_A0 UART receive data
PM_UCA0TXD 14 O Default mapping: eUSCI_A0 UART transmit data
PM_UCA1RXD 24 I Default mapping: eUSCI_A1 UART receive data
PM_UCA1TXD 25 O Default mapping: eUSCI_A1 UART transmit data
PM_UCA2RXD 35 I Default mapping: eUSCI_A2 UART receive data
PM_UCA2TXD 36 O Default mapping: eUSCI_A2 UART transmit data
(1) I = input, O = output
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE.
(3) TI recommends shorting unused analog input pairs and connect them to analog ground.
(4) The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
(5) When this pin is configured as reset, the internal pullup resistor is enabled by default.