JAJSG92D December 2011 – September 2018 MSP430F6720 , MSP430F6721 , MSP430F6723 , MSP430F6724 , MSP430F6725 , MSP430F6726 , MSP430F6730 , MSP430F6731 , MSP430F6733 , MSP430F6734 , MSP430F6735 , MSP430F6736
PRODUCTION DATA.
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage during program execution and flash programming, V(AVCC) = V(DVCC) = VCC(1)(2) | PMMCOREVx = 0 | 1.8 | 3.6 | V | |
PMMCOREVx = 0, 1 | 2.0 | 3.6 | ||||
PMMCOREVx = 0, 1, 2 | 2.2 | 3.6 | ||||
PMMCOREVx = 0, 1, 2, 3 | 2.4 | 3.6 | ||||
VSS | Supply voltage V(AVSS) = V(DVSS) = VSS | 0 | V | |||
TA | Operating free-air temperature | –40 | 85 | °C | ||
TJ | Operating junction temperature | –40 | 85 | °C | ||
CVCORE | Recommended capacitor at VCORE(3) | 470 | nF | |||
CDVCC/CVCORE | Capacitor ratio of DVCC to VCORE | 10 | ||||
fSYSTEM | Processor frequency (maximum MCLK frequency)(4)(5) (see Figure 5-1) | PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V (default condition) |
0 | 8.0 | MHz | |
PMMCOREVx = 1,
2.0 V ≤ VCC ≤ 3.6 V |
0 | 12.0 | ||||
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V |
0 | 20.0 | ||||
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V |
0 | 25.0 | ||||
ILOAD, DVCCD | Maximum load current that can be drawn from DVCC for core and IO
(ILOAD = ICORE + IIO) |
20 | mA | |||
ILOAD, AUX1D | Maximum load current that can be drawn from AUXVCC1 for core and IO
(ILOAD = ICORE + IIO) |
20 | mA | |||
ILOAD, AUX2D | Maximum load current that can be drawn from AUXVCC2 for core and IO
(ILOAD = ICORE + IIO) |
20 | mA | |||
ILOAD, AVCCA | Maximum load current that can be drawn from AVCC for analog modules
(ILOAD = IModules) |
10 | mA | |||
ILOAD, AUX1A | Maximum load current that can be drawn from AUXVCC1 for analog modules
(ILOAD = IModules) |
5 | mA | |||
ILOAD, AUX2A | Maximum load current that can be drawn from AUXVCC2 for analog modules
(ILOAD = IModules) |
5 | mA |