JAJSG94D November 2012 – September 2018 MSP430F67451 , MSP430F67461 , MSP430F67471 , MSP430F67481 , MSP430F67491 , MSP430F67651 , MSP430F67661 , MSP430F67671 , MSP430F67681 , MSP430F67691 , MSP430F67751 , MSP430F67761 , MSP430F67771 , MSP430F67781 , MSP430F67791
PRODUCTION DATA.
Figure 6-39 shows the port diagram. Table 6-96 summarizes the selection of the pin functions.
PIN NAME (PJ.x) | x | FUNCTION | CONTROL BITS OR SIGNALS(1) | |||
---|---|---|---|---|---|---|
PJDIR.x | PJSEL.x | JTAG MODE | ||||
PJ.0/SMCLK/TDO | 0 | PJ.0 (I/O)(1) | I: 0; O: 1 | 0 | 0 | |
SMCLK | 1 | 1 | 0 | |||
TDO(2) | x | x | 1 | |||
PJ.1/MCLK/TDI/TCLK | 1 | PJ.1 (I/O)(1) | I: 0; O: 1 | 0 | 0 | |
MCLK | 1 | 1 | 0 | |||
TDI/TCLK(2)(3) | x | x | 1 | |||
PJ.2/ADC10CLK/TMS | 2 | PJ.2 (I/O)(1) | I: 0; O: 1 | 0 | 0 | |
ADC10CLK | 1 | 1 | 0 | |||
TMS(2)(3) | x | x | 1 | |||
PJ.3/ACLK/TCK | 3 | PJ.3 (I/O)(1) | I: 0; O: 1 | 0 | 0 | |
ACLK | 1 | 1 | 0 | |||
TCK(2)(3) | x | x | 1 |