JAJSGB5A June   2014  – October 2018 MSP430F67621 , MSP430F67641

PRODUCTION DATA.  

1. 1デバイスの概要
   1. 1.1 特長
   2. 1.2 アプリケーション
   3. 1.3 概要
   4. 1.4 アプリケーション図
2. 2改訂履歴
3. 3Device Comparison
   1. 3.1 Related Products
4. 4Terminal Configuration and Functions
   1. 4.1 Pin Diagrams
   2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions – PZ Package
      2. Table 4-2 Signal Descriptions – PN Package
   3. 4.3 Pin Multiplexing
   4. 4.4 Connection of Unused Pins
5. 5Specifications
   1. 5.1 Absolute Maximum Ratings
   2. 5.2 ESD Ratings
   3. 5.3 Recommended Operating Conditions
   4. 5.4 Active Mode Supply Current Into VCC Excluding External Current
   5. 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
   6. 5.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
   7. 5.7 Thermal Resistance Characteristics
   8. 5.8 Timing and Switching Characteristics
      1. 5.8.1  Clock Specifications
         1. Table 5-1 Crystal Oscillator, XT1, Low-Frequency Mode
         2. Table 5-2 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
         3. Table 5-3 Internal Reference, Low-Frequency Oscillator (REFO)
         4. Table 5-4 DCO Frequency
      2. 5.8.2  Digital I/O Ports
         1. Table 5-5  Schmitt-Trigger Inputs – General-Purpose I/O
         2. Table 5-6  Inputs – Ports P1 and P2
         3. Table 5-7  Leakage Current – General-Purpose I/O
         4. Table 5-8  Outputs – General-Purpose I/O (Full Drive Strength)
         5. Table 5-9  Typical Characteristics – General-Purpose I/O (Full Drive Strength)
         6. Table 5-10 Outputs – General-Purpose I/O (Reduced Drive Strength)
         7. 5.8.2.1    Typical Characteristics – General-Purpose I/O (Reduced Drive Strength)
         8. Table 5-11 Output Frequency – General-Purpose I/O
      3. 5.8.3  Power-Management Module (PMM)
         1. Table 5-12 PMM, Brownout Reset (BOR)
         2. Table 5-13 PMM, Core Voltage
         3. Table 5-14 PMM, SVS High Side
         4. Table 5-15 PMM, SVM High Side
         5. Table 5-16 PMM, SVS Low Side
         6. Table 5-17 PMM, SVM Low Side
         7. Table 5-18 Wake-up Times From Low-Power Modes and Reset
      4. 5.8.4  Auxiliary Supplies
         1. Table 5-19 Auxiliary Supplies, Recommended Operating Conditions
         2. Table 5-20 Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents
         3. Table 5-21 Auxiliary Supplies, Auxiliary Supply Monitor
         4. Table 5-22 Auxiliary Supplies, Switch ON-Resistance
         5. Table 5-23 Auxiliary Supplies, Switching Time
         6. Table 5-24 Auxiliary Supplies, Switch Leakage
         7. Table 5-25 Auxiliary Supplies, Auxiliary Supplies to ADC10_A
         8. Table 5-26 Auxiliary Supplies, Charge Limiting Resistor
      5. 5.8.5  Timer_A
         1. Table 5-27 Timer_A
      6. 5.8.6  eUSCI
         1. Table 5-28 eUSCI (UART Mode) Clock Frequency
         2. Table 5-29 eUSCI (UART Mode) Switching Characteristics
         3. Table 5-30 eUSCI (SPI Master Mode) Clock Frequency
         4. Table 5-31 eUSCI (SPI Master Mode) Switching Characteristics
         5. Table 5-32 eUSCI (SPI Slave Mode)
         6. Table 5-33 eUSCI (I2C Mode)
      7. 5.8.7  LCD Controller
         1. Table 5-34 LCD_C Recommended Operating Conditions
         2. Table 5-35 LCD_C Electrical Characteristics
      8. 5.8.8  SD24_B
         1. Table 5-36 SD24_B Power Supply and Recommended Operating Conditions
         2. Table 5-37 SD24_B Analog Input
         3. Table 5-38 SD24_B Supply Currents
         4. Table 5-39 SD24_B Performance
         5. Table 5-40 SD24_B AC Performance
         6. Table 5-41 SD24_B AC Performance
         7. Table 5-42 SD24_B AC Performance
         8. Table 5-43 SD24_B External Reference Input
      9. 5.8.9  ADC10_A
         1. Table 5-44 10-Bit ADC, Power Supply and Input Range Conditions
         2. Table 5-45 10-Bit ADC, Timing Parameters
         3. Table 5-46 10-Bit ADC, Linearity Parameters
         4. Table 5-47 10-Bit ADC, External Reference
      10. 5.8.10 REF
          1. Table 5-48 REF, Built-In Reference
      11. 5.8.11 Flash Memory
          1. Table 5-49 Flash Memory
      12. 5.8.12 Emulation and Debug
          1. Table 5-50 JTAG and Spy-Bi-Wire Interface
6. 6Detailed Description
   1. 6.1  Overview
   2. 6.2  Functional Block Diagrams
   3. 6.3  CPU
   4. 6.4  Instruction Set
   5. 6.5  Operating Modes
   6. 6.6  Interrupt Vector Addresses
   7. 6.7  Memory Organization
   8. 6.8  Bootloader (BSL)
   9. 6.9  JTAG Operation
      1. 6.9.1 JTAG Standard Interface
      2. 6.9.2 Spy-Bi-Wire Interface
   10. 6.10 Flash Memory
   11. 6.11 RAM
   12. 6.12 Backup RAM
   13. 6.13 Peripherals
       1. 6.13.1  Oscillator and System Clock
       2. 6.13.2  Power Management Module (PMM)
       3. 6.13.3  Auxiliary Supply System (AUX)
       4. 6.13.4  Backup Subsystem
       5. 6.13.5  Digital I/O
       6. 6.13.6  Port Mapping Controller
       7. 6.13.7  System Module (SYS)
       8. 6.13.8  Watchdog Timer (WDT_A)
       9. 6.13.9  DMA Controller
       10. 6.13.10 CRC16
       11. 6.13.11 Hardware Multiplier
       12. 6.13.12 Enhanced Universal Serial Communication Interface (eUSCI)
       13. 6.13.13 ADC10_A
       14. 6.13.14 SD24_B
       15. 6.13.15 TA0
       16. 6.13.16 TA1
       17. 6.13.17 TA2
       18. 6.13.18 TA3
       19. 6.13.19 SD24_B Triggers
       20. 6.13.20 ADC10_A Triggers
       21. 6.13.21 Real-Time Clock (RTC_C)
       22. 6.13.22 Reference (REF) Module Voltage Reference
       23. 6.13.23 LCD_C
       24. 6.13.24 Embedded Emulation Module (EEM) (S Version)
       25. 6.13.25 Peripheral File Map
   14. 6.14 Input/Output Diagrams
       1. 6.14.1  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
       2. 6.14.2  Port P1 (P1.2), Input/Output With Schmitt Trigger
       3. 6.14.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
       4. 6.14.4  Port P1 (P1.6 and P1.7), Port P2 (P2.0 and P2.1) (PZ Package Only) Input/Output With Schmitt Trigger
       5. 6.14.5  Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (PZ Package Only)
       6. 6.14.6  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger (PZ Package Only)
       7. 6.14.7  Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger (PZ Package Only)
       8. 6.14.8  Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7), Port P7 (P7.0 to P7.7), Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger (PZ Package Only)
       9. 6.14.9  Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger (PZ Package Only)
       10. 6.14.10 Port P9 (P9.0) Input/Output With Schmitt Trigger (PZ Package Only)
       11. 6.14.11 Port P9 (P9.1 to P9.3) Input/Output With Schmitt Trigger (PZ Package Only)
       12. 6.14.12 Port P2 (P2.0 and P2.1) Input/Output With Schmitt Trigger (PN Package Only)
       13. 6.14.13 Port P2 (P2.2 to P2.7) Input/Output With Schmitt Trigger (PN Package Only)
       14. 6.14.14 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (PN Package Only)
       15. 6.14.15 Port P4 (P4.0 to P4.7), Port P5 (P5.0 to P5.7), Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (PN Package Only)
       16. 6.14.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
       17. 6.14.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
   15. 6.15 Device Descriptors (TLV)
   16. 6.16 Identification
       1. 6.16.1 Revision Identification
       2. 6.16.2 Device Identification
       3. 6.16.3 JTAG Identification
7. 7Applications, Implementation, and Layout
8. 8デバイスおよびドキュメントのサポート
   1. 8.1 使い始めと次の手順
   2. 8.2 Device Nomenclature
   3. 8.3 ツールとソフトウェア
   4. 8.4 ドキュメントのサポート
   5. 8.5 関連リンク
   6. 8.6 Community Resources
   7. 8.7 商標
   8. 8.8 静電気放電に関する注意事項
   9. 8.9 Glossary
9. 9メカニカル、パッケージ、および注文情報