JAJSG93E September   2012  – September 2018 MSP430F6745 , MSP430F6746 , MSP430F6747 , MSP430F6748 , MSP430F6749 , MSP430F6765 , MSP430F6766 , MSP430F6767 , MSP430F6768 , MSP430F6769 , MSP430F6775 , MSP430F6776 , MSP430F6777 , MSP430F6778 , MSP430F6779

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 アプリケーション図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-3 Terminal Functions – PEU Package
      2. Table 4-4 Terminal Functions – PZ Package
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 5.7  Thermal Packaging Characteristics
    8. 5.8  Schmitt-Trigger Inputs – General-Purpose I/O
    9. 5.9  Inputs – Ports P1 and P2
    10. 5.10 Leakage Current – General-Purpose I/O
    11. 5.11 Outputs – General-Purpose I/O (Full Drive Strength)
    12. 5.12 Outputs – General-Purpose I/O (Reduced Drive Strength)
    13. 5.13 Output Frequency – General-Purpose I/O
    14. 5.14 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    15. 5.15 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    16. 5.16 Crystal Oscillator, XT1, Low-Frequency Mode
    17. 5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 5.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 5.19 DCO Frequency
    20. 5.20 PMM, Brownout Reset (BOR)
    21. 5.21 PMM, Core Voltage
    22. 5.22 PMM, SVS High Side
    23. 5.23 PMM, SVM High Side
    24. 5.24 PMM, SVS Low Side
    25. 5.25 PMM, SVM Low Side
    26. 5.26 Wake-up Times From Low-Power Modes and Reset
    27. 5.27 Auxiliary Supplies Recommended Operating Conditions
    28. 5.28 Auxiliary Supplies, AUXVCC3 (Backup Subsystem) Currents
    29. 5.29 Auxiliary Supplies, Auxiliary Supply Monitor
    30. 5.30 Auxiliary Supplies, Switch ON-Resistance
    31. 5.31 Auxiliary Supplies, Switching Time
    32. 5.32 Auxiliary Supplies, Switch Leakage
    33. 5.33 Auxiliary Supplies, Auxiliary Supplies to ADC10_A
    34. 5.34 Auxiliary Supplies, Charge Limiting Resistor
    35. 5.35 Timer_A
    36. 5.36 eUSCI (UART Mode) Clock Frequency
    37. 5.37 eUSCI (UART Mode)
    38. 5.38 eUSCI (SPI Master Mode) Clock Frequency
    39. 5.39 eUSCI (SPI Master Mode)
    40. 5.40 eUSCI (SPI Slave Mode)
    41. 5.41 eUSCI (I2C Mode)
    42. 5.42 Schmitt-Trigger Inputs, RTC Tamper Detect Pin
    43. 5.43 Inputs, RTC Tamper Detect Pin
    44. 5.44 Leakage Current, RTC Tamper Detect Pin
    45. 5.45 Outputs, RTC Tamper Detect Pin
    46. 5.46 LCD_C Recommended Operating Conditions
    47. 5.47 LCD_C Electrical Characteristics
    48. 5.48 SD24_B Power Supply and Recommended Operating Conditions
    49. 5.49 SD24_B Analog Input
    50. 5.50 SD24_B Supply Currents
    51. 5.51 SD24_B Performance
    52. 5.52 SD24_B, AC Performance
    53. 5.53 SD24_B, AC Performance
    54. 5.54 SD24_B, AC Performance
    55. 5.55 SD24_B External Reference Input
    56. 5.56 10-Bit ADC Power Supply and Input Range Conditions
    57. 5.57 10-Bit ADC Switching Characteristics
    58. 5.58 10-Bit ADC Linearity Parameters
    59. 5.59 10-Bit ADC External Reference
    60. 5.60 REF Built-In Reference
    61. 5.61 Comparator_B
    62. 5.62 Flash Memory
    63. 5.63 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Functional Block Diagrams
    2. 6.2  CPU (Link to User's Guide)
    3. 6.3  Instruction Set
    4. 6.4  Operating Modes
    5. 6.5  Interrupt Vector Addresses
    6. 6.6  Special Function Registers (SFRs)
      1. Table 6-4 Interrupt Enable 1 Register Description
      2. Table 6-5 Interrupt Flag 1 Register Description
    7. 6.7  Memory Organization
    8. 6.8  Bootloader (BSL)
    9. 6.9  JTAG Operation
      1. 6.9.1 JTAG Standard Interface
      2. 6.9.2 Spy-Bi-Wire Interface
    10. 6.10 Flash Memory (Link to User's Guide)
    11. 6.11 RAM (Link to User's Guide)
    12. 6.12 Backup RAM (Link to User's Guide)
    13. 6.13 Peripherals
      1. 6.13.1  Oscillator and System Clock (Link to User's Guide)
      2. 6.13.2  Power-Management Module (PMM) (Link to User's Guide)
      3. 6.13.3  Auxiliary Supply System (Link to User's Guide)
      4. 6.13.4  Backup Subsystem
      5. 6.13.5  Digital I/O (Link to User's Guide)
      6. 6.13.6  Port Mapping Controller (Link to User's Guide)
      7. 6.13.7  System Module (SYS) (Link to User's Guide)
      8. 6.13.8  Watchdog Timer (WDT_A) (Link to User's Guide)
      9. 6.13.9  DMA Controller (Link to User's Guide)
      10. 6.13.10 CRC16 (Link to User's Guide)
      11. 6.13.11 Hardware Multiplier (Link to User's Guide)
      12. 6.13.12 AES128 Accelerator (Link to User's Guide)
      13. 6.13.13 Enhanced Universal Serial Communication Interface (eUSCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      14. 6.13.14 ADC10_A (Link to User's Guide)
      15. 6.13.15 SD24_B (Link to User's Guide)
      16. 6.13.16 TA0 (Link to User's Guide)
      17. 6.13.17 TA1 (Link to User's Guide)
      18. 6.13.18 TA2 (Link to User's Guide)
      19. 6.13.19 TA3 (Link to User's Guide)
      20. 6.13.20 SD24_B Triggers
      21. 6.13.21 ADC10_A Triggers
      22. 6.13.22 Real-Time Clock (RTC_C) (Link to User's Guide)
      23. 6.13.23 Reference Module (REF) Voltage Reference (Link to User's Guide)
      24. 6.13.24 LCD_C (Link to User's Guide)
      25. 6.13.25 Comparator_B (Link to User's Guide)
      26. 6.13.26 Embedded Emulation Module (EEM) (Link to User's Guide)
      27. 6.13.27 Peripheral File Map
    14. 6.14 Input/Output Diagrams
      1. 6.14.1  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      2. 6.14.2  Port P1 (P1.0 to P1.3) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      3. 6.14.3  Port P1 (P1.4 and P1.5) Input/Output With Schmitt Trigger (MSP430F677xIPEU and MSP430F677xIPZ)
      4. 6.14.4  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU and MSP430F677xIPZ)
      5. 6.14.5  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      6. 6.14.6  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      7. 6.14.7  Port P2 (P2.4 and P2.6) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      8. 6.14.8  Port P2 (P2.7) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      9. 6.14.9  Ports P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      10. 6.14.10 Ports P3 (P3.0) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      11. 6.14.11 Ports P3 (P3.1 to P3.7) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      12. 6.14.12 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      13. 6.14.13 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      14. 6.14.14 Port P5 (P5.0 to P5.3) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      15. 6.14.15 Port P5 (P5.4 to P5.6) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      16. 6.14.16 Port P5 (P5.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      17. 6.14.17 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      18. 6.14.18 Port P6 (P6.0) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      19. 6.14.19 Port P6 (P6.1 to P6.3) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      20. 6.14.20 Port P6 (P6.4 to P6.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      21. 6.14.21 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      22. 6.14.22 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger (MSP430F67xxIPEU Only)
      23. 6.14.23 Port P7 (P7.0 to P7.7) Input/Output With Schmitt Trigger (MSP430F67xxIPZ Only)
      24. 6.14.24 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      25. 6.14.25 Port P8 (P8.0) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      26. 6.14.26 Port P8 (P8.1) Input/Output With Schmitt Trigger (MSP430F677xIPZ Only)
      27. 6.14.27 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      28. 6.14.28 Port P10 (P10.0 to P10.7) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      29. 6.14.29 Port P11 (P11.0) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      30. 6.14.30 Port P11 (P11.1) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      31. 6.14.31 Port P11 (P11.2 and P11.3) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      32. 6.14.32 Port P11 (P11.4 and P11.5) Input/Output With Schmitt Trigger (MSP430F677xIPEU Only)
      33. 6.14.33 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      34. 6.14.34 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    15. 6.15 Device Descriptors (TLV)
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1  使い始めと次の手順
    2. 7.2  Device Nomenclature
    3. 7.3  ツールとソフトウェア
    4. 7.4  ドキュメントのサポート
    5. 7.5  関連リンク
    6. 7.6  Community Resources
    7. 7.7  商標
    8. 7.8  静電気放電に関する注意事項
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.2 Signal Descriptions

Table 4-3 describes the signals for devices in the PEU package. See Table 4-4 for the PZ package signal descriptions.

Table 4-3 Terminal Functions – PEU Package

TERMINAL I/O(1) DESCRIPTION
NAME NO.
PEU
XIN 1 I/O Input terminal for crystal oscillator
XOUT 2 I/O Output terminal for crystal oscillator
AUXVCC3 3 Auxiliary power supply AUXVCC3 for back up subsystem
RTCCAP1 4 I External time capture pin 1 for RTC_C
RTCCAP0 5 I External time capture pin 0 for RTC_C
P1.5/SMCLK/CB0/A5 6 I/O General-purpose digital I/O with port interrupt
SMCLK clock output
Comparator_B input CB0
Analog input A5 for 10-bit ADC
P1.4/MCLK/CB1/A4 7 I/O General-purpose digital I/O with port interrupt
MCLK clock output
Comparator_B input CB1
Analog input A4 for 10-bit ADC
P1.3/ADC10CLK/A3(3) 8 I/O General-purpose digital I/O with port interrupt
ADC10_A clock output
Analog input A3 for 10-bit ADC
P1.2/ACLK/A2 9 I/O General-purpose digital I/O with port interrupt
ACLK clock output
Analog input A2 for 10-bit ADC
P1.1/TA2.1/VeREF+/A1 10 I/O General-purpose digital I/O with port interrupt
Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output
Positive terminal for the ADC reference voltage for an external applied reference voltage
Analog input A1 for 10-bit ADC
P1.0/TA1.1/VeREF-/A0 11 I/O General-purpose digital I/O with port interrupt
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output
Negative terminal for the ADC reference voltage for an external applied reference voltage
Analog input A0 for 10-bit ADC
P2.4/PM_TA2.0 12 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
P2.5/PM_UCB0SOMI/ PM_UCB0SCL 13 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 SPI slave out master in

Default mapping: eUSCI_B0 I2C clock
P2.6/PM_UCB0SIMO/ PM_UCB0SDA 14 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 SPI slave in master out

Default mapping: eUSCI_B0 I2C data
P2.7/PM_UCB0CLK 15 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 clock input/output
P3.0/PM_UCA0RXD/ PM_UCA0SOMI 16 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A0 UART receive data

Default mapping: eUSCI_A0 SPI slave out master in
P3.1/PM_UCA0TXD/ PM_UCA0SIMO 17 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A0 UART transmit data

Default mapping: eUSCI_A0 SPI slave in master out
P3.2/PM_UCA0CLK 18 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A0 clock input/output
P3.3/PM_UCA1CLK 19 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A1 clock input/output
P3.4/PM_UCA1RXD/ PM_UCA1SOMI 20 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A1 UART receive data

Default mapping: eUSCI_A1 SPI slave out master in
P3.5/PM_UCA1TXD/ PM_UCA1SIMO 21 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A1 UART transmit data

Default mapping: eUSCI_A1 SPI slave in master out
COM0 22 O LCD common output COM0 for LCD backplane
COM1 23 O LCD common output COM1 for LCD backplane
P1.6/COM2 24 I/O General-purpose digital I/O with port interrupt

LCD common output COM2 for LCD backplane
P1.7/COM3 25 I/O General-purpose digital I/O with port interrupt

LCD common output COM3 for LCD backplane
P5.0/COM4 26 I/O General-purpose digital I/O

LCD common output COM4 for LCD backplane
P5.1/COM5 27 I/O General-purpose digital I/O

LCD common output COM5 for LCD backplane
P5.2/COM6 28 I/O General-purpose digital I/O

LCD common output COM6 for LCD backplane
P5.3/COM7 29 I/O General-purpose digital I/O

LCD common output COM7 for LCD backplane
LCDCAP/R33 30 I/O LCD capacitor connection

Input/output port of most positive analog LCD voltage (V1)

CAUTION: This pin must be connected to DVSS if not used.
P5.4/SDCLK/R23 31 I/O General-purpose digital I/O

SD24_B bit stream clock input/output

Input/output port of second most positive analog LCD voltage (V2)
P5.5/SD0DIO/ LCDREF/R13 32 I/O General-purpose digital I/O

SD24_B converter 0 bit stream data input/output

External reference voltage input for regulated LCD voltage

Input/output port of third most positive analog LCD voltage (V3 or V4)
P5.6/SD1DIO/R03 33 I/O General-purpose digital I/O

SD24_B converter 1 bit stream data input/output

Input/output port of lowest analog LCD voltage (V5)
P5.7/SD2DIO/CB2 34 I/O General-purpose digital I/O

SD24_B converter 2 bit stream data input/output

Comparator_B input CB2
P6.0/SD3DIO 35 I/O General-purpose digital I/O

SD24_B converter 3 bit stream data input/output
P3.6/PM_UCA2RXD/ PM_UCA2SOMI 36 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A2 UART receive data

Default mapping: eUSCI_A2 SPI slave out master in
P3.7/PM_UCA2TXD/ PM_UCA2SIMO 37 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A2 UART transmit data

Default mapping: eUSCI_A2 SPI slave in master out
P4.0/PM_UCA2CLK 38 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A2 clock input/output
P4.1/PM_UCA3RXD/ PM_UCA3SOMI 39 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A3 UART receive data

Default mapping: eUSCI_A3 SPI slave out master in
P4.2/PM_UCA3TXD/ PM_UCA3SIMO 40 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A3 UART transmit data

Default mapping: eUSCI_A3 SPI slave in master out
P4.3/PM_UCA3CLK 41 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A3 clock input/output
P4.4/PM_UCB1SOMI/ PM_UCB1SCL 42 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_B1 SPI slave out, master in

Default mapping: eUSCI_B1 I2C clock
P4.5/PM_UCB1SIMO/ PM_UCB1SDA 43 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_B1 SPI slave in, master out

Default mapping: eUSCI_B1 I2C data
P4.6/PM_UCB1CLK 44 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_B1 clock input/output
P4.7/PM_TA3.0 45 I/O General-purpose digital I/O with mappable secondary function

Default mapping: Timer TA3 capture CCR0: CCI0A input, compare: Out0 output
P6.1/SD4DIO/S39 46 I/O General-purpose digital I/O

SD24_B converter 4 bit stream data input/output (not available in F674x devices)

LCD segment output S39
P6.2/SD5DIO/S38 47 I/O General-purpose digital I/O

SD24_B converter 5 bit stream data input/output (not available in F674x devices)

LCD segment output S38
P6.3/SD6DIO/S37 48 I/O General-purpose digital I/O

SD24_B converter 6 bit stream data input/output (not available in F674x, F676x devices)

LCD segment output S37
P6.4/S36 49 I/O General-purpose digital I/O

LCD segment output S36
P6.5/S35 50 I/O General-purpose digital I/O

LCD segment output S35
P6.6/S34 51 I/O General-purpose digital I/O

LCD segment output S34
P6.7/S33 52 I/O General-purpose digital I/O

LCD segment output S33
P7.0/S32 53 I/O General-purpose digital I/O

LCD segment output S32
P7.1/S31 54 I/O General-purpose digital I/O

LCD segment output S31
P7.2/S30 55 I/O General-purpose digital I/O

LCD segment output S30
P7.3/S29 56 I/O General-purpose digital I/O

LCD segment output S29
P7.4/S28 57 I/O General-purpose digital I/O

LCD segment output S28
P7.5/S27 58 I/O General-purpose digital I/O

LCD segment output S27
P7.6/S26 59 I/O General-purpose digital I/O

LCD segment output S26
P7.7/S25 60 I/O General-purpose digital I/O

LCD segment output S25
P8.0/S24 61 I/O General-purpose digital I/O

LCD segment output S24
P8.1/S23 62 I/O General-purpose digital I/O

LCD segment output S23
P8.2/S22 63 I/O General-purpose digital I/O

LCD segment output S22
P8.3/S21 64 I/O General-purpose digital I/O

LCD segment output S21
P8.4/S20 65 I/O General-purpose digital I/O

LCD segment output S20
P8.5/S19 66 I/O General-purpose digital I/O

LCD segment output S19
P8.6/S18 67 I/O General-purpose digital I/O

LCD segment output S18
P8.7/S17 68 I/O General-purpose digital I/O

LCD segment output S17
VDSYS2(6) 69 Digital power supply for I/Os
DVSS2 70 Digital ground supply
P9.0/S16 71 I/O General-purpose digital I/O

LCD segment output S16
P9.1/S15 72 I/O General-purpose digital I/O

LCD segment output S15
P9.2/S14 73 I/O General-purpose digital I/O

LCD segment output S14
P9.3/S13 74 I/O General-purpose digital I/O

LCD segment output S13
P9.4/S12 75 I/O General-purpose digital I/O

LCD segment output S12
P9.5/S11 76 I/O General-purpose digital I/O

LCD segment output S11
P9.6/S10 77 I/O General-purpose digital I/O

LCD segment output S10
P9.7/S9 78 I/O General-purpose digital I/O

LCD segment output S9
P10.0/S8 79 I/O General-purpose digital I/O

LCD segment output S8
P10.1/S7 80 I/O General-purpose digital I/O

LCD segment output S7
P10.2/S6 81 I/O General-purpose digital I/O

LCD segment output S6
P10.3/S5 82 I/O General-purpose digital I/O

LCD segment output S5
P10.4/S4 83 I/O General-purpose digital I/O

LCD segment output S4
P10.5/S3 84 I/O General-purpose digital I/O

LCD segment output S3
P10.6/S2 85 I/O General-purpose digital I/O

LCD segment output S2
P10.7/S1 86 I/O General-purpose digital I/O

LCD segment output S1
P11.0/S0 87 I/O General-purpose digital I/O

LCD segment output S0
P11.1/TA3.1/CB3 88 I/O General-purpose digital I/O

Timer TA3 capture CCR1: CCI1A input, compare: Out1 output

Comparator_B input CB3
P11.2/TA1.1 89 I/O General-purpose digital I/O

Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
P11.3/TA2.1 90 I/O General-purpose digital I/O

Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
P11.4/CBOUT 91 I/O General-purpose digital I/O

Comparator_B Output
P11.5/TACLK/RTCCLK 92 I/O General-purpose digital I/O

Timer clock input TACLK for TA0, TA1, TA2, TA3

RTCCLK clock output
P2.0/PM_TA0.0/BSL_TX 93 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Timer TA0 capture CCR0: CCI0A input, compare: Out0 output

Bootloader: Data transmit
P2.1/PM_TA0.1/BSL_RX 94 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Timer TA0 capture CCR1: CCI1A input, compare: Out1 output

Bootloader: Data receive
P2.2/PM_TA0.2 95 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output
P2.3/PM_TA1.0 96 I/O General-purpose digital I/O port interrupt and with mappable secondary function

Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
TEST/SBWTCK 97 I Test mode pin – select digital I/O on JTAG pins

Spy-Bi-Wire input clock
PJ.0/TDO 98 I/O General-purpose digital I/O

Test data output
PJ.1/TDI/TCLK 99 I/O General-purpose digital I/O

Test data input or Test clock input
PJ.2/TMS 100 I/O General-purpose digital I/O

Test mode select
PJ.3/TCK 101 I/O General-purpose digital I/O

Test clock
RST/NMI/SBWTDIO 102 I/O Reset input active low(4)

Nonmaskable interrupt input

Spy-By-Wire data input/output
SD0P0 103 I SD24_B positive analog input for converter 0(5)
SD0N0 104 I SD24_B negative analog input for converter 0(5)
SD1P0 105 I SD24_B positive analog input for converter 1(5)
SD1N0 106 I SD24_B negative analog input for converter 1(5)
SD2P0 107 I SD24_B positive analog input for converter 2(5)
SD2N0 108 I SD24_B negative analog input for converter 2(5)
SD3P0 109 I SD24_B positive analog input for converter 3(5)
SD3N0 110 I SD24_B negative analog input for converter 3(4)
VASYS2 111 Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS
AVSS2 112 Analog ground supply
VREF 113 I SD24_B external reference voltage
SD4P0 114 I SD24_B positive analog input for converter 4(5) (not available on F674x devices)
SD4N0 115 I SD24_B negative analog input for converter 4(5) (not available on F674x devices)
SD5P0 116 I SD24_B positive analog input for converter 5(5) (not available on F674x devices)
SD5N0 117 I SD24_B negative analog input for converter 5(5) (not available on F674x devices)
SD6P0 118 I SD24_B positive analog input for converter 6(5) (not available on F676x, F674x devices)
SD6N0 119 I SD24_B negative analog input for converter 6(5) (not available on F676x, F674x devices)
AVSS1 120 Analog ground supply
AVCC 121 Analog power supply
VASYS1 122 Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS.
AUXVCC2 123 Auxiliary power supply AUXVCC2
AUXVCC1 124 Auxiliary power supply AUXVCC1
VDSYS1(6) 125 Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS.
DVCC 126 Digital power supply
DVSS1 127 Digital ground supply
VCORE(2) 128 Regulated core power supply (internal use only, no external current loading)
(1) I = input, O = output
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE.
(3) Before enabling the analog function (A3), pull this pin low by setting the port function to output low or to input with the internal pulldown resistor enabled.
(4) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(5) Short unused analog input pairs and connect them to analog ground.
(6) The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation.

Table 4-4 describes the signals for devices in the PZ package. See Table 4-3 for the PEU package signal descriptions.

Table 4-4 Terminal Functions – PZ Package

TERMINAL I/O(1) DESCRIPTION
NAME NO.
PZ
SD0P0 1 I SD24_B positive analog input for converter 0(2)
SD0N0 2 I SD24_B negative analog input for converter 0(2)
SD1P0 3 I SD24_B positive analog input for converter 1(2)
SD1N0 4 I SD24_B negative analog input for converter 1(2)
SD2P0 5 I SD24_B positive analog input for converter 2(2)
SD2N0 6 I SD24_B negative analog input for converter 2(2)
SD3P0 7 I SD24_B positive analog input for converter 3(2)
SD3N0 8 I SD24_B negative analog input for converter 3(2)
VASYS2 9 Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS.
AVSS2 10 Analog ground supply
VREF 11 I SD24_B external reference voltage
SD4P0 12 I SD24_B positive analog input for converter 4(2) (not available on F674x devices)
SD4N0 13 I SD24_B negative analog input for converter 4(2) (not available on F674x devices)
SD5P0 14 I SD24_B positive analog input for converter 5(2) (not available on F674x devices)
SD5N0 15 I SD24_B negative analog input for converter 5(2) (not available on F674x devices)
SD6P0 16 I SD24_B positive analog input for converter 6(2) (not available on F676x, F674x devices)
SD6N0 17 I SD24_B negative analog input for converter 6(2) (not available on F676x, F674x devices)
AVSS1 18 Analog ground supply
AVCC 19 Analog power supply
VASYS1 20 Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS
AUXVCC2 21 Auxiliary power supply AUXVCC2
AUXVCC1 22 Auxiliary power supply AUXVCC1
VDSYS1 (6) 23 Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended capacitor value of CVSYS.
DVCC 24 Digital power supply
DVSS1 25 Digital ground supply
VCORE (2) 26 Regulated core power supply (internal use only, no external current loading)
XIN 27 I/O Input terminal for crystal oscillator
XOUT 28 I/O Output terminal for crystal oscillator
AUXVCC3 29 Auxiliary power supply AUXVCC3 for back up subsystem
RTCCAP1 30 I External time capture pin 1 for RTC_C
RTCCAP0 31 I External time capture pin 0 for RTC_C
P1.5/SMCLK/CB0/A5 32 I/O General-purpose digital I/O with port interrupt

SMCLK clock output

Comparator_B input CB0

Analog input A5 for 10-bit ADC
P1.4/MCLK/CB1/A4 33 I/O General-purpose digital I/O with port interrupt

MCLK clock output

Comparator_B input CB1

Analog input A4 for 10-bit ADC
P1.3/ADC10CLK/A3 34 I/O General-purpose digital I/O with port interrupt

ADC10_A clock output

Analog input A3 for 10-bit ADC
P1.2/ACLK/A2 35 I/O General-purpose digital I/O with port interrupt

ACLK clock output

Analog input A2 for 10-bit ADC
P1.1/TA2.1/CBOUT/ VeREF+/A1 36 I/O General-purpose digital I/O with port interrupt

Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output

Comparator_B Output

Positive terminal for the ADC reference voltage for an external applied reference voltage

Analog input A1 for 10-bit ADC
P1.0/TA1.1/VeREF-/A0 37 I/O General-purpose digital I/O with port interrupt

Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output

Negative terminal for the ADC reference voltage for an external applied reference voltage

Analog input A0 for 10-bit ADC
COM0 38 I/O LCD common output COM0 for LCD backplane
COM1 39 I/O LCD common output COM1 for LCD backplane
P1.6/COM2 40 I/O General-purpose digital I/O with port interrupt

LCD common output COM2 for LCD backplane
P1.7/COM3 41 I/O General-purpose digital I/O with port interrupt

LCD common output COM3 for LCD backplane
P2.0/PM_TA0.0/ BSL_TX/COM4 42 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default Mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

Bootloader: Data transmit

LCD common output COM4 for LCD backplane
P2.1/PM_TA0.1/ BSL_RX/COM5 43 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default Mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output

Bootloader: Data receive

LCD common output COM5 for LCD backplane
P2.2/PM_TA0.2/COM6 44 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default Mapping: Timer TA0 CCR0 capture: CCI2A input, compare: Out2 output

LCD common output COM6 for LCD backplane
P2.3/PM_TA1.0/COM7 45 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default Mapping: Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output

LCD common output COM7 for LCD backplane
LCDCAP/R33 46 I/O LCD capacitor connection

Input/output port of most positive analog LCD voltage (V1)

CAUTION: This pin must be connected to DVSS if not used.
P2.4/PM_TA2.0/R23 47 I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default Mapping: Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output

Input/output port of second most positive analog LCD voltage (V2)
P2.5/PM_UCB0SOMI/ PM_UCB0SCL/LCDREF/ R13 48 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 SPI slave out, master in

Default mapping: eUSCI_B0 I2C clock

External reference voltage input for regulated LCD voltage

Input/output port of third most positive analog LCD voltage (V3 or V4)
P2.6/PM_UCB0SIMO/ PM_UCB0SDA/R03 49 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 SPI slave in, master out

Default mapping: eUSCI_B0 I2C data

Input/output port of lowest analog LCD voltage (V5)
P2.7/PM_UCB0CLK/CB2 50 I/O General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 clock input/output

Comparator_B input CB2
P3.0/PM_UCA0RXD/ PM_UCA0SOMI 51 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A0 UART receive data

Default mapping: eUSCI_A0 SPI slave out, master in
P3.1/PM_UCA0TXD/ PM_UCA0SIMO/S39 52 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A0 UART transmit data

Default mapping: eUSCI_A0 SPI slave in, master out

LCD segment output S39
P3.2/PM_UCA0CLK/S38 53 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A0 clock input/output

LCD segment output S38
P3.3/PM_UCA1CLK/S37 54 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A1 clock input/output

LCD segment output S37
P3.4/PM_UCA1RXD/ PM_UCA1SOMI/S36 55 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A1 UART receive data

Default mapping: eUSCI_A1 SPI slave out, master in

LCD segment output S36
P3.5/PM_UCA1TXD/ PM_UCA1SIMO/S35 56 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A1 UART transmit data

Default mapping: eUSCI_A1 SPI slave in, master out

LCD segment output S35
P3.6/PM_UCA2RXD/ PM_UCA2SOMI/S34 57 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A2 UART receive data

Default mapping: eUSCI_A2 SPI slave out, master in

LCD segment output S34
P3.7/PM_UCA2TXD/ PM_UCA2SIMO/S33 58 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A2 UART transmit data

Default mapping: eUSCI_A2 SPI slave in, master out

LCD segment output S33
P4.0/PM_UCA2CLK/S32 59 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A2 clock input/output

LCD segment output S32
P4.1/PM_UCA3RXD/ PM_UCA3SOMI/S31 60 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A3 UART receive data

Default mapping: eUSCI_A3 SPI slave out, master in

LCD segment output S31
P4.2/PM_UCA3TXD/ PM_UCA3SIMO/S30 61 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A3 UART transmit data

Default mapping: eUSCI_A3 SPI slave in, master out

LCD segment output S30
P4.3/PM_UCA3CLK/S29 62 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_A3 clock input/output

LCD segment output S29
P4.4/PM_UCB1SOMI/ PM_UCB1SCL/S28 63 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_B1 SPI slave out, master in

Default mapping: eUSCI_B1 I2C clock

LCD segment output S28
P4.5/PM_UCB1SIMO/ PM_UCB1SDA/S27 64 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_B1 SPI slave in, master out

Default mapping: eUSCI_B1 I2C data

LCD segment output S27
P4.6/PM_UCB1CLK/S26 65 I/O General-purpose digital I/O with mappable secondary function

Default mapping: eUSCI_B1 clock input/output

LCD segment output S26
P4.7/PM_TA3.0/S25 66 I/O

General-purpose digital I/O with mappable secondary function

Default Mapping: Timer TA3 CCR0 capture: CCI0A input, compare: Out0 output

LCD segment output S25
P5.0/SDCLK/S24 67 I/O General-purpose digital I/O

SD24_B bit stream clock input/output

LCD segment output S24
P5.1/PM_SD0DIO/S23 68 I/O General-purpose digital I/O

Default mapping: SD24_B converter 0 bit stream data input/output

LCD segment output S23
P5.2/PM_SD1DIO/S22 69 I/O General-purpose digital I/O

Default mapping: SD24_B converter 1 bit stream data input/output

LCD segment output S22
P5.3/PM_SD2DIO/S21 70 I/O General-purpose digital I/O

Default mapping: SD24_B converter 2 bit stream data input/output

LCD segment output S21
P5.4/PM_SD3DIO/S20 71 I/O General-purpose digital I/O

Default mapping: SD24_B converter 3 bit stream data input/output

LCD segment output S20
P5.5/PM_SD4DIO/S19 72 I/O General-purpose digital I/O

Default mapping: SD24_B converter 4 bit stream data input/output (not available on F674x devices)

LCD segment output S19
P5.6/PM_SD5DIO/S18 73 I/O General-purpose digital I/O

Default mapping: SD24_B converter 5 bit stream data input/output (not available on F674x devices)

LCD segment output S18
P5.7/PM_SD6DIO/S17 74 I/O General-purpose digital I/O

Default mapping: SD24_B converter 4 bit stream data input/output (not available on F676x, F674x devices)

LCD segment output S17
VDSYS2(3) 75 Digital power supply for I/Os
DVSS2 76 Digital ground supply
P6.0/S16 77 I/O General-purpose digital I/O

LCD segment output S16
P6.1/S15 78 I/O General-purpose digital I/O

LCD segment output S15
P6.2/S14 79 I/O General-purpose digital I/O

LCD segment output S14
P6.3/S13 80 I/O General-purpose digital I/O

LCD segment output S13
P6.4/S12 81 I/O General-purpose digital I/O

LCD segment output S12
P6.5/S11 82 I/O General-purpose digital I/O

LCD segment output S11
P6.6/S10 83 I/O General-purpose digital I/O

LCD segment output S10
P6.7/S9 84 I/O General-purpose digital I/O

LCD segment output S9
P7.0/S8 85 I/O General-purpose digital I/O

LCD segment output S8
P7.1/S7 86 I/O

General-purpose digital I/O

LCD segment output S7
P7.2/S6 87 I/O General-purpose digital I/O

LCD segment output S6
P7.3/S5 88 I/O

General-purpose digital I/O

LCD segment output S5
P7.4/S4 89 I/O General-purpose digital I/O

LCD segment output S4
P7.5/S3 90 I/O

General-purpose digital I/O

LCD segment output S3
P7.6/S2 91 I/O General-purpose digital I/O

LCD segment output S2
P7.7/S1 92 I/O General-purpose digital I/O

LCD segment output S1
P8.0/S0 93 I/O General-purpose digital I/O

LCD segment output S0
P8.1/TACLK/RTCCLK/CB3 94 I/O General-purpose digital I/O

Timer clock input TACLK for TA0, TA1, TA2, TA3

RTCCLK clock output

Comparator_B input CB3
TEST/SBWTCK 95 I Test mode pin – select digital I/O on JTAG pins

Spy-By-Wire input clock
PJ.0/TDO 96 I/O General-purpose digital I/O

Test data output
PJ.1/TDI/TCLK 97 I/O General-purpose digital I/O

Test data input or Test clock input
PJ.2/TMS 98 I/O General-purpose digital I/O

Test mode select
PJ.3/TCK 99 I/O General-purpose digital I/O

Test clock
RST/NMI/SBWTDIO 100 I/O Reset input, active low(4)

Nonmaskable interrupt input

Spy-By-Wire data input/output
(1) I = input, O = output
(2) Short unused analog input pairs and connect them to analog ground.
(3) The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation.