JAJSG93 データシート

Table 6-21 Peripherals

MODULE NAME	BASE ADDRESS	OFFSET ADDRESS RANGE
Special Functions (see Table 6-22)	0100h	000h to 01Fh
PMM (see Table 6-23)	0120h	000h to 01Fh
Flash Control (see Table 6-24)	0140h	000h to 00Fh
CRC16 (see Table 6-25)	0150h	000h to 007h
RAM Control (see Table 6-26)	0158h	000h to 001h
Watchdog (see Table 6-27)	015Ch	000h to 001h
UCS (see Table 6-28)	0160h	000h to 01Fh
SYS (see Table 6-29)	0180h	000h to 01Fh
Shared Reference (see Table 6-30)	01B0h	000h to 001h
Port Mapping Control (see Table 6-31)	01C0h	000h to 007h
Port Mapping Port P2 (see Table 6-32)	01D0h	000h to 007h
Port Mapping Port P3 (see Table 6-33)	01D8h	000h to 007h
Port Mapping Port P4 (see Table 6-34)	01E0h	000h to 007h
Port P1, P2 (see Table 6-35)	0200h	000h to 01Fh
Port P3, P4 (see Table 6-36)	0220h	000h to 00Bh
Port P5, P6 (see Table 6-37)	0240h	000h to 00Bh
Port P7, P8 (see Table 6-38)	0260h	000h to 00Bh
Port P9, P10 (see Table 6-39) (Ports P9 and P10 not available in PZ package)	0280h	000h to 00Bh
Port P11 (see Table 6-40) (Port P11 not available in PZ package)	02A0h	000h to 00Bh
Port PJ (see Table 6-41)	0320h	000h to 01Fh
Timer TA0 (see Table 6-42)	0340h	000h to 03Fh
Timer TA1 (see Table 6-43)	0380h	000h to 03Fh
Timer TA2 (see Table 6-44)	0400h	000h to 03Fh
Timer TA3 (see Table 6-45)	0440h	000h to 03Fh
Backup Memory (see Table 6-46)	0480h	000h to 00Fh
32-Bit Hardware Multiplier (see Table 6-48)	04C0h	000h to 02Fh
DMA General Control (see Table 6-49)	0500h	000h to 00Fh
DMA Channel 0 (see Table 6-50)	0500h	010h to 01Fh
DMA Channel 1 (see Table 6-51)	0500h	020h to 02Fh
DMA Channel 2 (see Table 6-52)	0500h	030h to 03Fh
RTC_C (see Table 6-47)	0C80h	000h to 03Fh
eUSCI_A0 (see Table 6-53)	05C0h	000h to 01Fh
eUSCI_A1 (see Table 6-54)	05E0h	000h to 01Fh
eUSCI_A2 (see Table 6-55)	0600h	000h to 01Fh
eUSCI_A3 (see Table 6-56)	0620h	000h to 01Fh
eUSCI_B0 (see Table 6-57)	0640h	000h to 02Fh
eUSCI_B1 ( see Table 6-58 )	0680h	000h to 02Fh
ADC10_A (see Table 6-59)	0740h	000h to 01Fh
SD24_B(see Table 6-60)	0800h	000h to 06Fh
Comparator_B (see Table 6-61 )	08C0h	000h to 00Fh
AES Accelerator (see Table 6-62)	09C0h	000h to 00Fh
Auxiliary Supply (see Table 6-63)	09E0h	000h to 01Fh
LCD_C (see Table 6-64)	0A00h	000h to 05Fh

Table 6-22 Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION	REGISTER	OFFSET
SFR interrupt enable	SFRIE1	00h
SFR interrupt flag	SFRIFG1	02h
SFR reset pin control	SFRRPCR	04h

Table 6-23 PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION	REGISTER	OFFSET
PMM control 0	PMMCTL0	00h
PMM control 1	PMMCTL1	02h
SVS high-side control	SVSMHCTL	04h
SVS low-side control	SVSMLCTL	06h
PMM interrupt flags	PMMIFG	0Ch
PMM interrupt enable	PMMIE	0Eh
PMM power mode 5 control register 0	PM5CTL0	10h

Table 6-24 Flash Control Registers (Base Address: 0140h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Flash control 1	FCTL1	00h
Flash control 3	FCTL3	04h
Flash control 4	FCTL4	06h

Table 6-25 CRC16 Registers (Base Address: 0150h)

REGISTER DESCRIPTION	REGISTER	OFFSET
CRC data input	CRC16DI	00h
CRC result	CRCINIRES	04h

Table 6-26 RAM Control Registers (Base Address: 0158h)

REGISTER DESCRIPTION	REGISTER	OFFSET
RAM control 0	RCCTL0	00h

Table 6-27 Watchdog Registers (Base Address: 015Ch)

REGISTER DESCRIPTION	REGISTER	OFFSET
Watchdog timer control	WDTCTL	00h

Table 6-28 UCS Registers (Base Address: 0160h)

REGISTER DESCRIPTION	REGISTER	OFFSET
UCS control 0	UCSCTL0	00h
UCS control 1	UCSCTL1	02h
UCS control 2	UCSCTL2	04h
UCS control 3	UCSCTL3	06h
UCS control 4	UCSCTL4	08h
UCS control 5	UCSCTL5	0Ah
UCS control 6	UCSCTL6	0Ch
UCS control 7	UCSCTL7	0Eh
UCS control 8	UCSCTL8	10h

Table 6-29 SYS Registers (Base Address: 0180h)

REGISTER DESCRIPTION	REGISTER	OFFSET
System control	SYSCTL	00h
Bootloader configuration area	SYSBSLC	02h
JTAG mailbox control	SYSJMBC	06h
JTAG mailbox input 0	SYSJMBI0	08h
JTAG mailbox input 1	SYSJMBI1	0Ah
JTAG mailbox output 0	SYSJMBO0	0Ch
JTAG mailbox output 1	SYSJMBO1	0Eh
Bus error vector generator	SYSBERRIV	18h
User NMI vector generator	SYSUNIV	1Ah
System NMI vector generator	SYSSNIV	1Ch
Reset vector generator	SYSRSTIV	1Eh

Table 6-30 Shared Reference Registers (Base Address: 01B0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Shared reference control	REFCTL	00h

Table 6-31 Port Mapping Controller (Base Address: 01C0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port mapping password	PMAPPWD	00h
Port mapping control	PMAPCTL	02h

Table 6-32 Port Mapping for Port P2 (Base Address: 01D0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P2.0 mapping	P2MAP0	00h
Port P2.1 mapping	P2MAP1	01h
Port P2.2 mapping	P2MAP2	02h
Port P2.3 mapping	P2MAP3	03h
Port P2.4 mapping	P2MAP4	04h
Port P2.5 mapping	P2MAP5	05h
Port P2.6 mapping	P2MAP6	06h
Port P2.7 mapping	P2MAP7	07h

Table 6-33 Port Mapping for Port P3 (Base Address: 01D8h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P3.0 mapping	P3MAP0	00h
Port P3.1 mapping	P3MAP1	01h
Port P3.2 mapping	P3MAP2	02h
Port P3.3 mapping	P3MAP3	03h
Port P3.4 mapping	P3MAP4	04h
Port P3.5 mapping	P3MAP5	05h
Port P3.6 mapping	P3MAP6	06h
Port P3.7 mapping	P3MAP7	07h

Table 6-34 Port Mapping for Port P4 (Base Address: 01E0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P4.0 mapping	P4MAP0	00h
Port P4.1 mapping	P4MAP1	01h
Port P4.2 mapping	P4MAP2	02h
Port P4.3 mapping	P4MAP3	03h
Port P4.4 mapping	P4MAP4	04h
Port P4.5 mapping	P4MAP5	05h
Port P4.6 mapping	P4MAP6	06h
Port P4.7 mapping	P4MAP7	07h

Table 6-35 Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P1 input	P1IN	00h
Port P1 output	P1OUT	02h
Port P1 direction	P1DIR	04h
Port P1 resistor enable	P1REN	06h
Port P1 drive strength	P1DS	08h
Port P1 selection 0	P1SEL0	0Ah
Port P1 selection 1	P1SEL1	0Ch
Port P1 interrupt vector word	P1IV	0Eh
Port P1 interrupt edge select	P1IES	18h
Port P1 interrupt enable	P1IE	1Ah
Port P1 interrupt flag	P1IFG	1Ch
Port P2 input	P2IN	01h
Port P2 output	P2OUT	03h
Port P2 direction	P2DIR	05h
Port P2 resistor enable	P2REN	07h
Port P2 drive strength	P2DS	09h
Port P2 selection 0	P2SEL0	0Bh
Port P2 selection 1⁽¹⁾	P2SEL1	0Dh
Port P2 interrupt vector word	P2IV	1Eh
Port P2 interrupt edge select	P2IES	19h
Port P2 interrupt enable	P2IE	1Bh
Port P2 interrupt flag	P2IFG	1Dh

(1) P2SEL1 is an empty control register to be consistent with P1SEL1 in 16-bit access.

Table 6-36 Port P3, P4 Registers (Base Address: 0220h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P3 input	P3IN	00h
Port P3 output	P3OUT	02h
Port P3 direction	P3DIR	04h
Port P3 resistor enable	P3REN	06h
Port P3 drive strength	P3DS	08h
Port P3 selection 0	P3SEL0	0Ah
Port P4 input	P4IN	01h
Port P4 output	P4OUT	03h
Port P4 direction	P4DIR	05h
Port P4 resistor enable	P4REN	07h
Port P4 drive strength	P4DS	09h
Port P4 selection 0	P4SEL0	0Bh

Table 6-37 Port P5, P6 Registers (Base Address: 0240h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P5 input	P5IN	00h
Port P5 output	P5OUT	02h
Port P5 direction	P5DIR	04h
Port P5 resistor enable	P5REN	06h
Port P5 drive strength	P5DS	08h
Port P5 selection 0	P5SEL0	0Ah
Port P5 selection 1	P5SEL1	0Ch
Port P6 input	P6IN	01h
Port P6 output	P6OUT	03h
Port P6 direction	P6DIR	05h
Port P6 resistor enable	P6REN	07h
Port P6 drive strength	P6DS	09h
Port P6 selection 0	P6SEL0	0Bh
Port P6 selection 1⁽¹⁾	P6SEL1	0Dh

(1) P6SEL1 is an empty control register to be consistent with P5SEL1 in 16-bit access.

Table 6-38 Port P7, P8 Registers (Base Address: 0260h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P7 input	P7IN	00h
Port P7 output	P7OUT	02h
Port P7 direction	P7DIR	04h
Port P7 resistor enable	P7REN	06h
Port P7 drive strength	P7DS	08h
Port P7 selection 0	P7SEL0	0Ah
Port P8 input	P8IN	01h
Port P8 output	P8OUT	03h
Port P8 direction	P8DIR	05h
Port P8 resistor enable	P8REN	07h
Port P8 drive strength	P8DS	09h
Port P8 selection 0	P8SEL0	0Bh

Table 6-39 Port P9, P10 Registers (Base Address: 0280h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P9 input	P9IN	00h
Port P9 output	P9OUT	02h
Port P9 direction	P9DIR	04h
Port P9 resistor enable	P9REN	06h
Port P9 drive strength	P9DS	08h
Port P9 selection 0	P9SEL0	0Ah
Port P10 input	P10IN	01h
Port P10 output	P10OUT	03h
Port P10 direction	P10DIR	05h
Port P10 resistor enable	P10REN	07h
Port P10 drive strength	P10DS	09h
Port P10 selection 0	P10SEL0	0Bh

Table 6-40 Port 11 Registers (Base Address: 02A0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port P11 input	P11IN	00h
Port P11 output	P11OUT	02h
Port P11 direction	P11DIR	04h
Port P11 resistor enable	P11REN	06h
Port P11 drive strength	P11DS	08h
Port P11 selection 0	P11SEL0	0Ah

Table 6-41 Port J Registers (Base Address: 0320h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Port PJ input	PJIN	00h
Port PJ output	PJOUT	02h
Port PJ direction	PJDIR	04h
Port PJ resistor enable	PJREN	06h
Port PJ drive strength	PJDS	08h
Port PJ selection	PJSEL	0Ah

Table 6-42 TA0 Registers (Base Address: 0340h)

REGISTER DESCRIPTION	REGISTER	OFFSET
TA0 control	TA0CTL	00h
Capture/compare control 0	TA0CCTL0	02h
Capture/compare control 1	TA0CCTL1	04h
Capture/compare control 2	TA0CCTL2	06h
TA0 counter	TA0R	10h
Capture/compare 0	TA0CCR0	12h
Capture/compare 1	TA0CCR1	14h
Capture/compare 2	TA0CCR2	16h
TA0 expansion 0	TA0EX0	20h
TA0 interrupt vector	TA0IV	2Eh

Table 6-43 TA1 Registers (Base Address: 0380h)

REGISTER DESCRIPTION	REGISTER	OFFSET
TA1 control	TA1CTL	00h
Capture/compare control 0	TA1CCTL0	02h
Capture/compare control 1	TA1CCTL1	04h
TA1 counter	TA1R	10h
Capture/compare 0	TA1CCR0	12h
Capture/compare 1	TA1CCR1	14h
TA1 expansion 0	TA1EX0	20h
TA1 interrupt vector	TA1IV	2Eh

Table 6-44 TA2 Registers (Base Address: 0400h)

REGISTER DESCRIPTION	REGISTER	OFFSET
TA2 control	TA2CTL	00h
Capture/compare control 0	TA2CCTL0	02h
Capture/compare control 1	TA2CCTL1	04h
TA2 counter	TA2R	10h
Capture/compare 0	TA2CCR0	12h
Capture/compare 1	TA2CCR1	14h
TA2 expansion 0	TA2EX0	20h
TA2 interrupt vector	TA2IV	2Eh

Table 6-45 TA3 Registers (Base Address: 0440h)

REGISTER DESCRIPTION	REGISTER	OFFSET
TA3 control	TA3CTL	00h
Capture/compare control 0	TA3CCTL0	02h
Capture/compare control 1	TA3CCTL1	04h
TA3 counter	TA3R	10h
Capture/compare 0	TA3CCR0	12h
Capture/compare 1	TA3CCR1	14h
TA3 expansion 0	TA3EX0	20h
TA3 interrupt vector	TA3IV	2Eh

Table 6-46 Backup Memory Registers (Base Address: 0480h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Backup memory 0	BAKMEM0	00h
Backup memory 1	BAKMEM1	02h
Backup memory 2	BAKMEM2	04h
Backup memory 3	BAKMEM3	06h

Table 6-47 RTC_C Registers (Base Address: 0C80h)

REGISTER DESCRIPTION	REGISTER	OFFSET
RTC control 0	RTCCTL0	00h
RTC password	RTCPWD	01h
RTC control 1	RTCCTL1	02h
RTC control 3	RTCCTL3	03h
RTC offset calibration	RTCOCAL	04h
RTC temperature compensation	RTCTCMP	06h
RTC prescaler 0 control	RTCPS0CTL	08h
RTC prescaler 1 control	RTCPS1CTL	0Ah
RTC prescaler 0	RTCPS0	0Ch
RTC prescaler 1	RTCPS1	0Dh
RTC interrupt vector word	RTCIV	0Eh
RTC seconds	RTCSEC	10h
RTC minutes	RTCMIN	11h
RTC hours	RTCHOUR	12h
RTC day of week	RTCDOW	13h
RTC days	RTCDAY	14h
RTC month	RTCMON	15h
RTC year	RTCYEAR	16h
RTC alarm minutes	RTCAMIN	18h
RTC alarm hours	RTCAHOUR	19h
RTC alarm day of week	RTCADOW	1Ah
RTC alarm days	RTCADAY	1Bh
Binary-to-BCD conversion	BIN2BCD	1Ch
BCD-to-Binary conversion	BCD2BIN	1Eh
Real-Time Clock Time Capture Control Register	RTCTCCTL	20h
Tamper Detect Pin 0 Control Register	RTCCAP0CTL	21h
Tamper Detect Pin 1 Control Register	RTCCAP1CTL	22h
RTC seconds Backup Register 0	RTCSECBAK0	30h
RTC minutes Backup Register 0	RTCMINBAK0	31h
RTC hours Backup Register 0	RTCHOURBAK0	32h
RTC days Backup Register 0	RTCDAYBAK0	33h
RTC month Backup Register 0	RTCMONBAK0	34h
RTC year Backup Register 0	RTCYEARBAK0	36h
RTC seconds Backup Register 1	RTCSECBAK1	38h
RTC minutes Backup Register 1	RTCMINBAK1	39h
RTC hours Backup Register 1	RTCHOURBAK1	3Ah
RTC days Backup Register 1	RTCDAYBAK1	3Bh
RTC month Backup Register 1	RTCMONBAK1	3Ch
RTC year Backup Register 1	RTCYEARBAK1	3Eh

Table 6-48 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
16-bit operand 1 – multiply	MPY	00h
16-bit operand 1 – signed multiply	MPYS	02h
16-bit operand 1 – multiply accumulate	MAC	04h
16-bit operand 1 – signed multiply accumulate	MACS	06h
16-bit operand 2	OP2	08h
16 × 16 result low word	RESLO	0Ah
16 × 16 result high word	RESHI	0Ch
16 × 16 sum extension	SUMEXT	0Eh
32-bit operand 1 – multiply low word	MPY32L	10h
32-bit operand 1 – multiply high word	MPY32H	12h
32-bit operand 1 – signed multiply low word	MPYS32L	14h
32-bit operand 1 – signed multiply high word	MPYS32H	16h
32-bit operand 1 – multiply accumulate low word	MAC32L	18h
32-bit operand 1 – multiply accumulate high word	MAC32H	1Ah
32-bit operand 1 – signed multiply accumulate low word	MACS32L	1Ch
32-bit operand 1 – signed multiply accumulate high word	MACS32H	1Eh
32-bit operand 2 – low word	OP2L	20h
32-bit operand 2 – high word	OP2H	22h
32 × 32 result 0 – least significant word	RES0	24h
32 × 32 result 1	RES1	26h
32 × 32 result 2	RES2	28h
32 × 32 result 3 – most significant word	RES3	2Ah
MPY32 control 0	MPY32CTL0	2Ch

Table 6-49 DMA General Control Registers (Base Address: 0500h)

REGISTER DESCRIPTION	REGISTER	OFFSET
DMA module control 0	DMACTL0	00h
DMA module control 1	DMACTL1	02h
DMA module control 2	DMACTL2	04h
DMA module control 3	DMACTL3	06h
DMA module control 4	DMACTL4	08h
DMA interrupt vector	DMAIV	0Eh

Table 6-50 DMA Channel 0 Registers (Base Address: 0500h)

REGISTER DESCRIPTION	REGISTER	OFFSET
DMA channel 0 control	DMA0CTL	10h
DMA channel 0 source address low	DMA0SAL	12h
DMA channel 0 source address high	DMA0SAH	14h
DMA channel 0 destination address low	DMA0DAL	16h
DMA channel 0 destination address high	DMA0DAH	18h
DMA channel 0 transfer size	DMA0SZ	1Ah

Table 6-51 DMA Channel 1 Registers (Base Address: 0500h)

REGISTER DESCRIPTION	REGISTER	OFFSET
DMA channel 1 control	DMA1CTL	20h
DMA channel 1 source address low	DMA1SAL	22h
DMA channel 1 source address high	DMA1SAH	24h
DMA channel 1 destination address low	DMA1DAL	26h
DMA channel 1 destination address high	DMA1DAH	28h
DMA channel 1 transfer size	DMA1SZ	2Ah

Table 6-52 DMA Channel 2 Registers (Base Address: 0500h)

REGISTER DESCRIPTION	REGISTER	OFFSET
DMA channel 2 control	DMA2CTL	30h
DMA channel 2 source address low	DMA2SAL	32h
DMA channel 2 source address high	DMA2SAH	34h
DMA channel 2 destination address low	DMA2DAL	36h
DMA channel 2 destination address high	DMA2DAH	38h
DMA channel 2 transfer size	DMA2SZ	3Ah

Table 6-53 eUSCI_A0 Registers (Base Address: 05C0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
USCI_A control word 0	UCA0CTLW0	00h
USCI _A control word 1	UCA0CTLW1	02h
USCI_A baud rate 0	UCA0BR0	06h
USCI_A baud rate 1	UCA0BR1	07h
USCI_A modulation control	UCA0MCTLW	08h
USCI_A status	UCA0STAT	0Ah
USCI_A receive buffer	UCA0RXBUF	0Ch
USCI_A transmit buffer	UCA0TXBUF	0Eh
USCI_A LIN control	UCA0ABCTL	10h
USCI_A IrDA transmit control	UCA0IRTCTL	12h
USCI_A IrDA receive control	UCA0IRRCTL	13h
USCI_A interrupt enable	UCA0IE	1Ah
USCI_A interrupt flags	UCA0IFG	1Ch
USCI_A interrupt vector word	UCA0IV	1Eh

Table 6-54 eUSCI_A1 Registers (Base Address:05E0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
USCI_A control word 0	UCA1CTLW0	00h
USCI _A control word 1	UCA1CTLW1	02h
USCI_A baud rate 0	UCA1BR0	06h
USCI_A baud rate 1	UCA1BR1	07h
USCI_A modulation control	UCA1MCTLW	08h
USCI_A status	UCA1STAT	0Ah
USCI_A receive buffer	UCA1RXBUF	0Ch
USCI_A transmit buffer	UCA1TXBUF	0Eh
USCI_A LIN control	UCA1ABCTL	10h
USCI_A IrDA transmit control	UCA1IRTCTL	12h
USCI_A IrDA receive control	UCA1IRRCTL	13h
USCI_A interrupt enable	UCA1IE	1Ah
USCI_A interrupt flags	UCA1IFG	1Ch
USCI_A interrupt vector word	UCA1IV	1Eh

Table 6-55 eUSCI_A2 Registers (Base Address:0600h)

REGISTER DESCRIPTION	REGISTER	OFFSET
USCI_A control word 0	UCA2CTLW0	00h
USCI _A control word 1	UCA2CTLW1	02h
USCI_A baud rate 0	UCA2BR0	06h
USCI_A baud rate 1	UCA2BR1	07h
USCI_A modulation control	UCA2MCTLW	08h
USCI_A status	UCA2STAT	0Ah
USCI_A receive buffer	UCA2RXBUF	0Ch
USCI_A transmit buffer	UCA2TXBUF	0Eh
USCI_A LIN control	UCA2ABCTL	10h
USCI_A IrDA transmit control	UCA2IRTCTL	12h
USCI_A IrDA receive control	UCA2IRRCTL	13h
USCI_A interrupt enable	UCA2IE	1Ah
USCI_A interrupt flags	UCA2IFG	1Ch
USCI_A interrupt vector word	UCA2IV	1Eh

Table 6-56 eUSCI_A3 Registers (Base Address: 0620h)

REGISTER DESCRIPTION	REGISTER	OFFSET
USCI_A control word 0	UCA3CTLW0	00h
USCI _A control word 1	UCA3CTLW1	02h
USCI_A baud rate 0	UCA3BR0	06h
USCI_A baud rate 1	UCA3BR1	07h
USCI_A modulation control	UCA3MCTLW	08h
USCI_A status	UCA3STAT	0Ah
USCI_A receive buffer	UCA3RXBUF	0Ch
USCI_A transmit buffer	UCA3TXBUF	0Eh
USCI_A LIN control	UCA3ABCTL	10h
USCI_A IrDA transmit control	UCA3IRTCTL	12h
USCI_A IrDA receive control	UCA3IRRCTL	13h
USCI_A interrupt enable	UCA3IE	1Ah
USCI_A interrupt flags	UCA3IFG	1Ch
USCI_A interrupt vector word	UCA3IV	1Eh

Table 6-57 eUSCI_B0 Registers (Base Address: 0640h)

REGISTER DESCRIPTION	REGISTER	OFFSET
USCI_B control word 0	UCB0CTLW0	00h
USCI_B control word 1	UCB0CTLW1	02h
USCI_B bit rate 0	UCB0BR0	06h
USCI_B bit rate 1	UCB0BR1	07h
USCI_B status word	UCB0STATW	08h
USCI_B byte counter threshold	UCB0TBCNT	0Ah
USCI_B receive buffer	UCB0RXBUF	0Ch
USCI_B transmit buffer	UCB0TXBUF	0Eh
USCI_B I2C own address 0	UCB0I2COA0	14h
USCI_B I2C own address 1	UCB0I2COA1	16h
USCI_B I2C own address 2	UCB0I2COA2	18h
USCI_B I2C own address 3	UCB0I2COA3	1Ah
USCI_B received address	UCB0ADDRX	1Ch
USCI_B address mask	UCB0ADDMASK	1Eh
USCI I2C slave address	UCB0I2CSA	20h
USCI interrupt enable	UCB0IE	2Ah
USCI interrupt flags	UCB0IFG	2Ch
USCI interrupt vector word	UCB0IV	2Eh

Table 6-58 eUSCI_B1 Registers (Base Address: 0680h)

REGISTER DESCRIPTION	REGISTER	OFFSET
USCI_B control word 0	UCB1CTLW0	00h
USCI_B control word 1	UCB1CTLW1	02h
USCI_B bit rate 0	UCB1BR0	06h
USCI_B bit rate 1	UCB1BR1	07h
USCI_B status word	UCB1STATW	08h
USCI_B byte counter threshold	UCB1TBCNT	0Ah
USCI_B receive buffer	UCB1RXBUF	0Ch
USCI_B transmit buffer	UCB1TXBUF	0Eh
USCI_B I2C own address 0	UCB1I2COA0	14h
USCI_B I2C own address 1	UCB1I2COA1	16h
USCI_B I2C own address 2	UCB1I2COA2	18h
USCI_B I2C own address 3	UCB1I2COA3	1Ah
USCI_B received address	UCB1ADDRX	1Ch
USCI_B address mask	UCB1ADDMASK	1Eh
USCI I2C slave address	UCB1I2CSA	20h
USCI interrupt enable	UCB1IE	2Ah
USCI interrupt flags	UCB1IFG	2Ch
USCI interrupt vector word	UCB1IV	2Eh

Table 6-59 ADC10_A Registers (Base Address: 0740h)

REGISTER DESCRIPTION	REGISTER	OFFSET
ADC10_A control 0	ADC10CTL0	00h
ADC10_A control 1	ADC10CTL1	02h
ADC10_A control 2	ADC10CTL2	04h
ADC10_A window comparator low threshold	ADC10LO	06h
ADC10_A window comparator high threshold	ADC10HI	08h
ADC10_A memory control 0	ADC10MCTL0	0Ah
ADC10_A conversion memory	ADC10MCTL0	12h
ADC10_A interrupt enable	ADC10IE	1Ah
ADC10_A interrupt flags	ADC10IGH	1Ch
ADC10_A interrupt vector word	ADC10IV	1Eh

Table 6-60 SD24_B Registers (Base Address: 0800h)

REGISTER DESCRIPTION	REGISTER	OFFSET
SD24_B control 0	SD24BCTL0	00h
SD24_B control 1	SD24BCTL1	02h
SD24_B trigger control	SD24BTRGCTL	04h
SD24_B trigger OSR control	SD24BTRGOSR	06h
SD24_B trigger preload	SD24BTRGPRE	08h
SD24_B interrupt flag	SD24BIFG	0Ah
SD24_B interrupt enable	SD24BIE	0Ch
SD24_B interrupt vector	SD24BIV	0Eh
SD24_B converter 0 control	SD24BCCTL0	10h
SD24_B converter 0 input control	SD24BINCTL0	12h
SD24_B converter 0 OSR control	SD24BOSR0	14h
SD24_B converter 0 preload	SD24BPRE0	16h
SD24_B converter 1 control	SD24BCCTL1	18h
SD24_B converter 1 input control	SD24BINCTL1	1Ah
SD24_B converter 1 OSR control	SD24BOSR1	1Ch
SD24_B converter 1 preload	SD24BPRE1	1Eh
SD24_B converter 2 control	SD24BCCTL2	20h
SD24_B converter 2 input control	SD24BINCTL2	22h
SD24_B converter 2 OSR control	SD24BOSR2	24h
SD24_B converter 2 preload	SD24BPRE2	26h
SD24_B converter 3 control	SD24BCCTL3	28h
SD24_B converter 3 input control	SD24BINCTL3	2Ah
SD24_B converter 3 OSR control	SD24BOSR3	2Ch
SD24_B converter 3 preload	SD24BPRE3	2Eh
SD24_B converter 4 control	SD24BCCTL4	30h
SD24_B converter 4 input control	SD24BINCTL4	32h
SD24_B converter 4 OSR control	SD24BOSR4	34h
SD24_B converter 4 preload	SD24BPRE4	36h
SD24_B converter 5 control	SD24BCCTL5	38h
SD24_B converter 5 input control	SD24BINCTL5	3Ah
SD24_B converter 5 OSR control	SD24BOSR5	3Ch
SD24_B converter 5 preload	SD24BPRE5	3Eh
SD24_B converter 6 control	SD24BCCTL6	40h
SD24_B converter 6 input control	SD24BINCTL6	42h
SD24_B converter 6 OSR control	SD24BOSR6	44h
SD24_B converter 6 preload	SD24BPRE6	46h
SD24_B converter 0 conversion memory low word	SD24BMEML0	50h
SD24_B converter 0 conversion memory high word	SD24BMEMH0	52h
SD24_B converter 1 conversion memory low word	SD24BMEML1	54h
SD24_B converter 1 conversion memory high word	SD24BMEMH1	56h
SD24_B converter 2 conversion memory low word	SD24BMEML2	58h
SD24_B converter 2 conversion memory high word	SD24BMEMH2	5Ah
SD24_B converter 3 conversion memory low word	SD24BMEML3	5Ch
SD24_B converter 3 conversion memory high word	SD24BMEMH3	5Eh
SD24_B converter 4 conversion memory low word	SD24BMEML4	60h
SD24_B converter 4 conversion memory high word	SD24BMEMH4	62h
SD24_B converter 5 conversion memory low word	SD24BMEML5	64h
SD24_B converter 5 conversion memory high word	SD24BMEMH5	66h
SD24_B converter 6 conversion memory low word	SD24BMEML6	68h
SD24_B converter 6 conversion memory high word	SD24BMEMH6	6Ah

Table 6-61 Comparator_B Register (Base Address: 08C0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Comp_B control 0	CBCTL0	00h
Comp_B control 1	CBCTL1	02h
Comp_B control 2	CBCTL2	04h
Comp_B control 3	CBCTL3	06h
Comp_B interrupt	CBINT	0Ch
Comp_B interrupt vector word	CBIV	0Eh

Table 6-62 AES Accelerator Registers (Base Address: 09C0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
AES accelerator control 0	AESACTL0	00h
AES accelerator status	AESASTAT	04h
AES accelerator key	AESAKEY	06h
AES accelerator data in	AESADIN	08h
AES accelerator data out	AESADOUT	0Ah

Table 6-63 Auxiliary Supply Registers (Base Address: 09E0h)

REGISTER DESCRIPTION	REGISTER	OFFSET
Auxiliary supply control 0	AUXCTL0	00h
Auxiliary supply control 1	AUXCTL1	02h
Auxiliary supply control 2	AUXCTL2	04h
AUX2 charger control	AUX2CHCTL	12h
AUX3 charger control	AUX3CHCTL	14h
AUX ADC control	AUXADCCTL	16h
AUX interrupt flag	AUXIFG	1Ah
AUX interrupt enable	AUXIE	1Ch
AUX interrupt vector word	AUXIV	1Eh

Table 6-64 LCD_C Registers (Base Address: 0A00h)

REGISTER DESCRIPTION	REGISTER	OFFSET
LCD_C control 0	LCDCCTL0	000h
LCD_C control 1	LCDCCTL1	002h
LCD_C blinking control	LCDCBLKCTL	004h
LCD_C memory control	LCDCMEMCTL	006h
LCD_C voltage control	LCDCVCTL	008h
LCD_C port control 0	LCDCPCTL0	00Ah
LCD_C port control 1	LCDCPCTL1	00Ch
LCD_C port control 2	LCDCPCTL2	00Eh
LCD_C charge pump control	LCDCCPCTL	012h
LCD_C interrupt vector	LCDCIV	01Eh
Static and 2 to 4 mux modes
LCD_C memory 1	LCDM1	020h
LCD_C memory 2	LCDM2	021h
⋮	⋮	⋮
LCD_C memory 20	LCDM20	033h
LCD_C blinking memory 1	LCDBM1	040h
LCD_C blinking memory 2	LCDBM2	041h
⋮	⋮	⋮
LCD_C blinking memory 20	LCDBM20	053h
5 to 8 mux modes
LCD_C memory 1	LCDM1	020h
LCD_C memory 2	LCDM2	021h
⋮	⋮	⋮
LCD_C memory 40	LCDM40	047h

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

サーマルパッド・メカニカル・データ

発注情報

6.13.27 Peripheral File Map

Table 6-21 Peripherals

Table 6-22 Special Function Registers (Base Address: 0100h)

Table 6-23 PMM Registers (Base Address: 0120h)

Table 6-24 Flash Control Registers (Base Address: 0140h)

Table 6-25 CRC16 Registers (Base Address: 0150h)

Table 6-26 RAM Control Registers (Base Address: 0158h)

Table 6-27 Watchdog Registers (Base Address: 015Ch)

Table 6-28 UCS Registers (Base Address: 0160h)

Table 6-29 SYS Registers (Base Address: 0180h)

Table 6-30 Shared Reference Registers (Base Address: 01B0h)

Table 6-31 Port Mapping Controller (Base Address: 01C0h)

Table 6-32 Port Mapping for Port P2 (Base Address: 01D0h)

Table 6-33 Port Mapping for Port P3 (Base Address: 01D8h)

Table 6-34 Port Mapping for Port P4 (Base Address: 01E0h)

Table 6-35 Port P1, P2 Registers (Base Address: 0200h)

Table 6-36 Port P3, P4 Registers (Base Address: 0220h)

Table 6-37 Port P5, P6 Registers (Base Address: 0240h)

Table 6-38 Port P7, P8 Registers (Base Address: 0260h)

Table 6-39 Port P9, P10 Registers (Base Address: 0280h)

Table 6-40 Port 11 Registers (Base Address: 02A0h)

Table 6-41 Port J Registers (Base Address: 0320h)

Table 6-42 TA0 Registers (Base Address: 0340h)

Table 6-43 TA1 Registers (Base Address: 0380h)

Table 6-44 TA2 Registers (Base Address: 0400h)

Table 6-45 TA3 Registers (Base Address: 0440h)

Table 6-46 Backup Memory Registers (Base Address: 0480h)

Table 6-47 RTC_C Registers (Base Address: 0C80h)

Table 6-48 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

Table 6-49 DMA General Control Registers (Base Address: 0500h)

Table 6-50 DMA Channel 0 Registers (Base Address: 0500h)

Table 6-51 DMA Channel 1 Registers (Base Address: 0500h)

Table 6-52 DMA Channel 2 Registers (Base Address: 0500h)

Table 6-53 eUSCI_A0 Registers (Base Address: 05C0h)

Table 6-54 eUSCI_A1 Registers (Base Address:05E0h)

Table 6-55 eUSCI_A2 Registers (Base Address:0600h)

Table 6-56 eUSCI_A3 Registers (Base Address: 0620h)

Table 6-57 eUSCI_B0 Registers (Base Address: 0640h)

Table 6-58 eUSCI_B1 Registers (Base Address: 0680h)

Table 6-59 ADC10_A Registers (Base Address: 0740h)

Table 6-60 SD24_B Registers (Base Address: 0800h)

Table 6-61 Comparator_B Register (Base Address: 08C0h)

Table 6-62 AES Accelerator Registers (Base Address: 09C0h)

Table 6-63 Auxiliary Supply Registers (Base Address: 09E0h)

Table 6-64 LCD_C Registers (Base Address: 0A00h)