JAJSG96 データシート

JAJSG96A May 2014 – September 2018 MSP430F67451A , MSP430F67461A , MSP430F67471A , MSP430F67481A , MSP430F67491A , MSP430F67651A , MSP430F67661A , MSP430F67671A , MSP430F67681A , MSP430F67691A , MSP430F67751A , MSP430F67761A , MSP430F67771A , MSP430F67781A , MSP430F67791A

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PEU|128
- MPQF058B
PZ|100
- MTQF013A

サーマルパッド・メカニカル・データ

PZ|100
- QFND428

発注情報

6.6 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 6-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6-3 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE	INTERRUPT FLAG	SYSTEM INTERRUPT	WORD ADDRESS	PRIORITY
System Reset Power up External reset Watchdog time-out, key violation Flash memory key violation	WDTIFG, KEYV (SYSRSTIV)⁽¹⁾⁽²⁾	Reset	0FFFEh	63, highest
System NMI PMM Vacant memory access JTAG mailbox	SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBINIFG, JMBOUTIFG (SYSSNIV) ⁽¹⁾⁽³⁾	(Non)maskable	0FFFCh	62
User NMI NMI Oscillator fault Flash memory access violation Supply switched	NMIIFG, OFIFG, ACCVIFG, AUXSWGIFG (SYSUNIV)⁽¹⁾⁽³⁾	(Non)maskable	0FFFAh	61
Watchdog Timer_A interval timer mode	WDTIFG	Maskable	0FFF8h	60
eUSCI_A0 receive or transmit	UCA0RXIFG, UCA0TXIFG (UCA0IV)⁽¹⁾⁽⁴⁾	Maskable	0FFF6h	59
eUSCI_B0 receive or transmit	UCB0RXIFG, UCB0TXIFG (UCB0IV)⁽¹⁾⁽⁴⁾	Maskable	0FFF4h	58
ADC10_A	ADC10IFG0, ADC10INIFG, ADC10LOIFG, ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG (ADC10IV)⁽¹⁾⁽⁴⁾	Maskable	0FFF2h	57
SD24_B	SD24_B Interrupt Flags (SD24IV)⁽¹⁾⁽⁴⁾	Maskable	0FFF0h	56
Timer TA0	TA0CCR0 CCIFG0⁽⁴⁾	Maskable	0FFEEh	55
Timer TA0	TA0CCR1 CCIFG1, TA0CCR2 CCIFG2, TA0IFG (TA0IV)⁽¹⁾⁽⁴⁾	Maskable	0FFECh	54
eUSCI_A1 receive or transmit	UCA1RXIFG, UCA1TXIFG (UCA1IV)⁽¹⁾⁽⁴⁾	Maskable	0FFEAh	53
eUSCI_A2 receive or transmit	UCA2RXIFG, UCA2TXIFG (UCA2IV)⁽¹⁾⁽⁴⁾	Maskable	0FFE8h	52
Auxiliary supplies	AUXSWGIFG, AUXIFG0, AUXIFG1, AUXIFG2 (AUXIV)⁽¹⁾⁽⁴⁾	Maskable	0FFE6h	51
DMA	DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)⁽¹⁾⁽⁴⁾	Maskable	0FFE4h	50
Timer TA1	TA1CCR0 CCIFG0⁽⁴⁾	Maskable	0FFE2h	49
Timer TA1	TA1CCR1 CCIFG1, TA1IFG (TA1IV)⁽¹⁾⁽⁴⁾	Maskable	0FFE0h	48
eUSCI_A3 receive or transmit	UCA3RXIFG, UCA3TXIFG (UCA3IV)⁽¹⁾⁽⁴⁾	Maskable	0FFDEh	47
eUSCI_B1 receive or transmit	UCB1RXIFG, UCB1TXIFG (UCB1IV)⁽¹⁾⁽⁴⁾	Maskable	0FFDCh	46
I/O port P1	P1IFG.0 to P1IFG.7 (P1IV)⁽¹⁾⁽⁴⁾	Maskable	0FFDAh	45
Timer TA2	TA2CCR0 CCIFG0⁽⁴⁾	Maskable	0FFD8h	44
Timer TA2	TA2CCR1 CCIFG1, TA2IFG (TA2IV)⁽¹⁾⁽⁴⁾	Maskable	0FFD6h	43
I/O port P2	P2IFG.0 to P2IFG.7 (P2IV)⁽¹⁾⁽⁴⁾	Maskable	0FFD4h	42
Timer TA3	TA3CCR0 CCIFG0⁽⁴⁾	Maskable	0FFD2h	41
Timer TA3	TA3CCR1 CCIFG1, TA3IFG (TA3IV)⁽¹⁾⁽⁴⁾	Maskable	0FFD0h	40
LCD_C	LCD_C Interrupt Flags (LCDCIV)⁽¹⁾⁽⁴⁾	Maskable	0FFCEh	39
RTC_C	RTCOFIFG, RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV)⁽¹⁾⁽⁴⁾	Maskable	0FFCCh	38
Comparator_B	Comparator_B Interrupt Flags (CBIV) ⁽¹⁾	Maskable	0FFCAh	37
Reserved	Reserved⁽⁵⁾		0FFC6h	35
			⋮	⋮
			0FF80h	0, lowest

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(3) (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.

(4) Interrupt flags are in the module.

(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations.