ZHCSCI3 数据表 | 德州仪器 TI.com.cn

JAJSG96A May 2014 – September 2018 MSP430F67451A , MSP430F67461A , MSP430F67471A , MSP430F67481A , MSP430F67491A , MSP430F67651A , MSP430F67661A , MSP430F67671A , MSP430F67681A , MSP430F67691A , MSP430F67751A , MSP430F67761A , MSP430F67771A , MSP430F67781A , MSP430F67791A

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PEU|128
- MPQF058B
PZ|100
- MTQF013A

サーマルパッド・メカニカル・データ

PZ|100
- QFND428

発注情報

Table 5-30 eUSCI (SPI Master Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE low to clock	UCSTEM = 0, UCMODEx = 01 or 10	2 V, 3 V	150		ns
t_STE,LEAD	STE lead time, STE low to clock	UCSTEM = 1, UCMODEx = 01 or 10	2 V, 3 V	150		ns
t_STE,LAG	STE lag time, Last clock to STE high	UCSTEM = 0, UCMODEx = 01 or 10	2 V, 3 V	200		ns
t_STE,LAG	STE lag time, Last clock to STE high	UCSTEM = 1, UCMODEx = 01 or 10	2 V, 3 V	200		ns
t_STE,ACC	STE access time, STE low to SIMO data out	UCSTEM = 0, UCMODEx = 01 or 10	2 V		50	ns
		UCSTEM = 0, UCMODEx = 01 or 10	3 V		30
		UCSTEM = 1, UCMODEx = 01 or 10	2 V		50
		UCSTEM = 1, UCMODEx = 01 or 10	3 V		30
t_STE,DIS	STE disable time, STE high to SIMO high impedance	UCSTEM = 0, UCMODEx = 01 or 10	2 V		40	ns
		UCSTEM = 0, UCMODEx = 01 or 10	3 V		25
		UCSTEM = 1, UCMODEx = 01 or 10	2 V		40
		UCSTEM = 1, UCMODEx = 01 or 10	3 V		25
t_SU,MI	SOMI input data setup time		2 V	50		ns
t_SU,MI	SOMI input data setup time		3 V	30		ns
t_HD,MI	SOMI input data hold time		2 V	0		ns
t_HD,MI	SOMI input data hold time		3 V	0		ns
t_VALID,MO	SIMO output data valid time⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	2 V		9	ns
t_VALID,MO	SIMO output data valid time⁽²⁾	UCLK edge to SIMO valid, C_L = 20 pF	3 V		5	ns
t_HD,MO	SIMO output data hold time⁽³⁾	C_L = 20 pF	2 V	0		ns
t_HD,MO	SIMO output data hold time⁽³⁾	C_L = 20 pF	3 V	0		ns

(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)})
For the slave parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-11 and Figure 5-12.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-11 and Figure 5-12.

MSP430F67791A MSP430F67781A MSP430F67771A MSP430F67761A MSP430F67751A MSP430F67691A MSP430F67681A MSP430F67671A MSP430F67661A MSP430F67651A MSP430F67491A MSP430F67481A MSP430F67471A MSP430F67461A MSP430F67451A slas639-eUSCI_master_CKPH0.gif

Figure 5-11 SPI Master Mode, CKPH = 0

Figure 5-12 SPI Master Mode, CKPH = 1

Table 5-31 lists the characteristics of the eUSCI in SPI slave mode.