Table 5-42 SD24_B, Performance
fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1
| PARAMETER |
TEST CONDITIONS |
VCC |
MIN |
TYP |
MAX |
UNIT |
| INL |
Integral nonlinearity, end-point fit |
SD24GAIN: 1 |
3 V |
–0.01 |
|
+0.01 |
% of FSR |
| SD24GAIN: 8 |
–0.01 |
|
+0.01 |
| SD24GAIN: 32 |
–0.01 |
|
+0.01 |
| Gnom |
Nominal gain |
SD24GAIN: 1 |
3 V |
|
1 |
|
|
| SD24GAIN: 2 |
|
2 |
|
| SD24GAIN: 4 |
|
4 |
|
| SD24GAIN: 8 |
|
8 |
|
| SD24GAIN: 16 |
|
16 |
|
| SD24GAIN: 32 |
|
32 |
|
| SD24GAIN: 64 |
|
64 |
|
| SD24GAIN: 128 |
|
128 |
|
| EG |
Gain error(1) |
SD24GAIN: 1, with external reference (1.2 V) |
3 V |
–1% |
|
+1% |
|
| SD24GAIN: 8, with external reference (1.2 V) |
–2% |
|
+2% |
| SD24GAIN: 32, with external reference (1.2 V) |
–2% |
|
+2% |
| ΔEG/ΔT |
Gain error temperature coefficient(2), internal reference |
SD24GAIN: 1, 8, or 32 (with internal reference) |
3 V |
|
|
80 |
ppm/°C |
| ΔEG/ΔT |
Gain error temperature coefficient(2), external reference |
SD24GAIN: 1 (with external reference) |
3 V |
|
|
15 |
ppm/°C |
| SD24GAIN: 8 (with external reference) |
|
|
15 |
| SD24GAIN: 32 (with external reference) |
|
|
15 |
| ΔEG/ΔVCC |
Gain error vs VCC(3) |
SD24GAIN: 1 |
3 V |
|
0.1 |
|
%/V |
| SD24GAIN: 8 |
|
0.1 |
|
| SD24GAIN: 32 |
|
0.4 |
|
| EOS[V] |
Offset error(4) |
SD24GAIN: 1 (with Vdiff = 0 V) |
3 V |
|
|
2.3 |
mV |
| SD24GAIN: 8 |
|
|
1 |
| SD24GAIN: 32 |
|
|
0.5 |
| EOS[FS] |
Offset error(4) |
SD24GAIN: 1 (with Vdiff = 0 V) |
3 V |
–0.2 |
|
+0.2 |
% FS |
| SD24GAIN: 8 |
–0.7 |
|
+0.7 |
| SD24GAIN: 32 |
–1.4 |
|
+1.4 |
| ΔEOS/ΔT |
Offset error temperature coefficient(5) |
SD24GAIN: 1 |
3 V |
|
2 |
|
µV/°C |
| SD24GAIN: 8 |
|
0.25 |
|
| SD24GAIN: 32 |
|
0.1 |
|
| ΔEOS/ΔVCC |
Offset error vs VCC(6) |
SD24GAIN: 1 |
3 V |
|
500 |
|
µV/V |
| SD24GAIN: 8 |
|
125 |
|
| SD24GAIN: 32 |
|
50 |
|
| CMRR,DC |
Common-mode rejection at DC(7) |
SD24GAIN: 1 |
3 V |
|
–120 |
|
dB |
| SD24GAIN: 8 |
|
–110 |
|
| SD24GAIN: 32 |
|
–100 |
|
| CMRR,50Hz |
Common-mode rejection at 50 Hz(8) |
SD24GAIN: 1, fCM = 50 Hz, VCM = 930 mV |
3 V |
|
–120 |
|
dB |
| SD24GAIN: 8, fCM = 50 Hz, VCM = 120 mV |
|
–110 |
|
| SD24GAIN: 32, fCM = 50 Hz, VCM = 30 mV |
|
–100 |
|
| AC PSRR, ext |
AC power supply rejection ratio, external reference(9) |
SD24GAIN: 1, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz |
|
|
–61 |
|
dB |
| SD24GAIN: 8, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz |
|
–75 |
|
| SD24GAIN: 32, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz |
|
–79 |
|
| AC PSRR, int |
AC power supply rejection ratio, internal reference(9) |
SD24GAIN: 1, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz |
|
|
–61 |
|
dB |
| SD24GAIN: 8, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz |
|
–75 |
|
| SD24GAIN: 32, VCC = 3 V + 50 mV × sin(2π × fVCC × t), fVCC = 50 Hz |
|
–79 |
|
| XT |
Crosstalk between converters(10) |
Crosstalk source: SD24GAIN: 1, Sine-wave with maximum possible Vpp, fIN = 50 Hz or 100 Hz, Converter under test: SD24GAIN: 1 |
3 V |
|
–120 |
|
dB |
| Crosstalk source: SD24GAIN: 1, Sine-wave with maximum possible Vpp, fIN = 50 Hz or 100 Hz, Converter under test: SD24GAIN: 8 |
|
–115 |
|
| Crosstalk source: SD24GAIN: 1, Sine-wave with maximum possible Vpp, fIN = 50 Hz or 100 Hz, Converter under test: SD24GAIN: 32 |
|
–110 |
|
(1) The gain error EG specifies the deviation of the actual gain Gact from the nominal gain Gnom: EG = (Gact – Gnom)/Gnom. It covers process, temperature, and supply voltage variations.
(2) The gain error temperature coefficient ΔEG/ ΔT specifies the variation of the gain error EG over temperature (EG(T) = (Gact(T) – Gnom)/Gnom) using the box method (that is, minimum and maximum values):
ΔEG/ ΔT = (MAX(EG(T)) – MIN(EG(T) ) / (MAX(T) – MIN(T)) = (MAX(Gact(T)) – MIN(Gact(T)) / Gnom / (MAX(T) – MIN(T))
with T ranging from –40°C to 85°C.
(3) The gain error vs VCC coefficient ΔEG/ ΔVCC specifies the variation of the gain error EG over supply voltage (EG(VCC) = (Gact(VCC) – Gnom)/Gnom) using the box method (that is, minimum and maximum values):
ΔEG/ ΔVCC = (MAX(EG(VCC)) – MIN(EG(VCC) ) / (MAX(VCC) – MIN(VCC)) = (MAX(Gact(VCC)) – MIN(Gact(VCC)) / Gnom / (MAX(VCC) – MIN(VCC))
with VCC ranging from 2.4 V to 3.6 V.
(4) The offset error EOS is measured with shorted inputs in 2s-complement mode with +100% FS = VREF/G and –100% FS = –VREF/G.
Conversion between EOS [FS] and EOS [V] is as follows: EOS [FS] = EOS [V] × G/VREF, EOS [V] = EOS [FS] × VREF/G.
(5) The offset error temperature coefficient ΔEOS/ ΔT specifies the variation of the offset error EOS over temperature using the box method (that is, minimum and maximum values):
ΔEOS/ ΔT = (MAX(EOS(T)) – MIN(EOS(T) ) / (MAX(T) – MIN(T))
with T ranging from –40°C to 85°C.
(6) The offset error vs VCC ΔEOS/ ΔVCC specifies the variation of the offset error EOS over supply voltage using the box method (that is, minimum and maximum values):
ΔEOS/ ΔVCC = (MAX(EOS(VCC)) – MIN(EOS(VCC) ) / (MAX(VCC) – MIN(VCC))
with VCC ranging from 2.4 V to 3.6 V.
(7) The DC CMRR specifies the change in the measured differential input voltage value when the common-mode voltage varies:
DC CMRR = –20log(ΔMAX/FSR) with ΔMAX being the difference between the minium value and the maximum value measured when sweeping the common-mode voltage.
The DC CMRR is measured with both inputs connected to the common-mode voltage (that is, no differential input signal is applied), and the common-mode voltage is swept from –1 V to VCC.
(8) The AC CMRR is the difference between a hypothetical signal with the amplitude and frequency of the applied common-mode ripple applied to the inputs of the ADC and the actual common-mode signal spur visible in the FFT spectrum:
AC CMRR = Error Spur [dBFS] – 20log(VCM / 1.2 V / G) [dBFS] with a common-mode signal of VCM × sin(2π × fCM × t) applied to the analog inputs.
The AC CMRR is measured with the both inputs connected to the common-mode signal; that is, no differential input signal is applied.
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
(9) The AC PSRR is the difference between a hypothetical signal with the amplitude and frequency of the applied supply voltage ripple applied to the inputs of the ADC and the actual supply ripple spur visible in the FFT spectrum:
AC PSRR = Error Spur [dBFS] – 20log(50 mV / 1.2 V / G) [dBFS] with a signal of 50 mV × sin(2π × fVCC × t) added to VCC.
The AC PSRR is measured with the inputs grounded; that is, no analog input signal is applied.
With the specified typical values the error spur is within the noise floor (as specified by the SINAD values).
SD24GAIN: 1 → Hypothetical signal: 20log(50 mV / 1.2 V / 1) = –27.6 dBFS
SD24GAIN: 8 → Hypothetical signal: 20log(50 mV / 1.2 V / 8) = –9.5 dBFS
SD24GAIN: 32 → Hypothetical signal: 20log(50 mV / 1.2 V / 32) = 2.5 dBFS
(10) The crosstalk XT is specified as the tone level of the signal applied to the crosstalk source seen in the spectrum of the converter under test. It is measured with the inputs of the converter under test being grounded.
Table 5-43 lists the AC performance characteristics of the SD24_B.