SLAS508K April   2006  – May 2020 MSP430FG4616 , MSP430FG4617 , MSP430FG4618 , MSP430FG4619

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Supply Current Into AVCC + DVCC Excluding External Current
    5. 5.5  Thermal Characteristics
    6. 5.6  Schmitt-Trigger Inputs – Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)
    7. 5.7  Inputs Px.x, TAx, TBX
    8. 5.8  Leakage Current – Ports P1 to P10
    9. 5.9  Outputs – Ports P1 to P10
    10. 5.10 Output Frequency
    11. 5.11 Typical Characteristics – Outputs
    12. 5.12 Wake-up Timing From LPM3
    13. 5.13 RAM
    14. 5.14 LCD_A
    15. 5.15 Comparator_A
    16. 5.16 Typical Characteristics – Comparator_A
    17. 5.17 POR, BOR
    18. 5.18 SVS (Supply Voltage Supervisor and Monitor)
    19. 5.19 DCO
    20. 5.20 Crystal Oscillator, LFXT1 Oscillator
    21. 5.21 Crystal Oscillator, XT2 Oscillator
    22. 5.22 USCI (UART Mode)
    23. 5.23 USCI (SPI Master Mode)
    24. 5.24 USCI (SPI Slave Mode)
    25. 5.25 USCI (I2C Mode)
    26. 5.26 USART1
    27. 5.27 12-Bit ADC, Power Supply and Input Range Conditions
    28. 5.28 12-Bit ADC, External Reference
    29. 5.29 12-Bit ADC, Built-In Reference
    30. 5.30 12-Bit ADC, Timing Parameters
    31. 5.31 12-Bit ADC, Linearity Parameters
    32. 5.32 12-Bit ADC, Temperature Sensor and Built-In VMID
    33. 5.33 12-Bit DAC, Supply Specifications
    34. 5.34 12-Bit DAC, Linearity Specifications
    35. 5.35 12-Bit DAC, Output Specifications
    36. 5.36 12-Bit DAC, Reference Input Specifications
    37. 5.37 12-Bit DAC, Dynamic Specifications
    38. 5.38 12-Bit DAC, Dynamic Specifications Continued
    39. 5.39 Operational Amplifier OA, Supply Specifications
    40. 5.40 Operational Amplifier OA, Input/Output Specifications
    41. 5.41 Operational Amplifier OA, Dynamic Specifications
    42. 5.42 Operational Amplifier OA, Typical Characteristics
    43. 5.43 Operational Amplifier OA Feedback Network, Noninverting Amplifier Mode (OAFCx = 4)
    44. 5.44 Operational Amplifier OA Feedback Network, Inverting Amplifier Mode (OAFCx = 6)
    45. 5.45 Flash Memory (FG461x Devices Only)
    46. 5.46 JTAG Interface
    47. 5.47 JTAG Fuse
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Special Function Registers (SFRs)
      1. 6.5.1 Interrupt Enable 1 and 2
      2. 6.5.2 Interrupt Flag Register 1 and 2
      3. 6.5.3 Module Enable Registers 1 and 2
    6. 6.6  Memory Organization
    7. 6.7  Bootstrap Loader (BSL)
    8. 6.8  Flash Memory
    9. 6.9  Peripherals
      1. 6.9.1  DMA Controller
      2. 6.9.2  Oscillator and System Clock
      3. 6.9.3  Brownout, Supply Voltage Supervisor (SVS)
      4. 6.9.4  Digital I/O
      5. 6.9.5  Basic Timer1 and Real-Time Clock
      6. 6.9.6  LCD_A Drive With Regulated Charge Pump
      7. 6.9.7  Watchdog Timer (WDT+)
      8. 6.9.8  Universal Serial Communication Interface (USCI)
      9. 6.9.9  USART1
      10. 6.9.10 Hardware Multiplier
      11. 6.9.11 Timer_A3
      12. 6.9.12 Timer_B7
      13. 6.9.13 Comparator_A
      14. 6.9.14 ADC12
      15. 6.9.15 DAC12
      16. 6.9.16 OA
      17. 6.9.17 Peripheral File Map
    10. 6.10 Input/Output Schematics
      1. 6.10.1  Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1, P1.6, P1.7, Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2, P2.0 to P2.3, P2.6 to P2.7, Input/Output With Schmitt Trigger
      4. 6.10.4  Port P2, P2.4 to P2.5, Input/Output With Schmitt Trigger
      5. 6.10.5  Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
      7. 6.10.7  Port P4, P4.0 to P4.1, Input/Output With Schmitt Trigger
      8. 6.10.8  Port P4, P4.2 to P4.7, Input/Output With Schmitt Trigger
      9. 6.10.9  Port P5, P5.0, Input/Output With Schmitt Trigger
      10. 6.10.10 Port P5, P5.1, Input/Output With Schmitt Trigger
      11. 6.10.11 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger
      12. 6.10.12 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger
      13. 6.10.13 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger
      14. 6.10.14 Port P6, P6.1, P6.3, and P6.5 Input/Output With Schmitt Trigger
      15. 6.10.15 Port P6, P6.6, Input/Output With Schmitt Trigger
      16. 6.10.16 Port P6, P6.7, Input/Output With Schmitt Trigger
      17. 6.10.17 Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger
      18. 6.10.18 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      19. 6.10.19 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
      20. 6.10.20 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
      21. 6.10.21 Port P10, P10.0 to P10.5, Input/Output With Schmitt Trigger
      22. 6.10.22 Port P10, P10.6, Input/Output With Schmitt Trigger
      23. 6.10.23 Port P10, P10.7, Input/Output With Schmitt Trigger
      24. 6.10.24 VeREF+/DAC0
      25. 6.10.25 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
      26. 6.10.26 JTAG Fuse Check Mode
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Getting Started and Next Steps
      2. 7.1.2 Development Tools Support
        1. 7.1.2.1 Hardware Features
        2. 7.1.2.2 Recommended Hardware Options
          1. 7.1.2.2.1 Target Socket Boards
          2. 7.1.2.2.2 Experimenter Boards
          3. 7.1.2.2.3 Debugging and Programming Tools
          4. 7.1.2.2.4 Production Programmers
        3. 7.1.2.3 Recommended Software Options
          1. 7.1.2.3.1 Integrated Development Environments
          2. 7.1.2.3.2 MSP430Ware
          3. 7.1.2.3.3 Command-Line Programmer
      3. 7.1.3 Device Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Related Links
    4. 7.4 Community Resources
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.29 12-Bit ADC, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF+ Positive built in reference voltage output REF2_5V = 1 for 2.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min		 VCC = 3 V 2.4 2.5 2.6 V
REF2_5V = 0 for 1.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min		 VCC = 2.2 V, 3 V 1.44 1.5 1.56
AVCC(min) AVCC minimum voltage, Positive built in reference active REF2_5V = 0, IVREF+max ≤ IVREF+ ≤ IVREF+min 2.2 V
REF2_5V = 1, IVREF+min ≥ IVREF+ ≥ –0.5 mA 2.8
REF2_5V = 1, IVREF+min ≥ IVREF+ ≥ – 1 mA 2.9
IVREF+ Load current out of VREF+ terminal VCC = 2.2 V 0.01 –0.5 mA
VCC = 3 V 0.01 –1
IL(VREF+) Load-current regulation, VREF+ terminal IVREF+ = 500 µA ±100 µA,
Analog input voltage ≈ 0.75 V,
REF2_5V = 0		 VCC = 2.2 V ±2 LSB
VCC = 3 V ±2
IVREF+ = 500 µA ±100 µA,
Analog input voltage ≈ 1.25 V,
REF2_5V = 1		 VCC = 3 V ±2
IDL(VREF+) Load current regulation, VREF+ terminal IVREF+ = 100 µA → 900 µA,
CVREF+ = 5 µF, Ax ≈ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB		 VCC = 3 V 20 ns
CVREF+ Capacitance at pin VREF+(1) REFON = 1,
0 mA ≤ IVREF+ ≤ IVREF+max		 VCC = 2.2 V, 3 V 5 10 µF
TREF+ Temperature coefficient of built-in reference IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ 1 mA		 VCC = 2.2 V, 3 V ±100 ppm/°C
tREFON Settling time of internal reference voltage (see Figure 5-23 ) (2) IVREF+ = 0.5 mA, CVREF+ = 10 µF,
VREF+ = 1.5 V, VAVCC = 2.2 V 		17 ms
(1) The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF-–/VeREF– and AVSS: 10-µF tantalum and 100-nF ceramic.
(2) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external capacitive load.
MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_typ_settime_extcap.gifFigure 5-23 Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_supvol_refvol_ext.gifFigure 5-24 Supply Voltage and Reference Voltage Design VREF–/VeREF– External Supply
MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619 MSP430CG4618 MSP430CG4617 MSP430CG4616 slas508_supvol_refvol_internal.gifFigure 5-25 Supply Voltage and Reference Voltage Design VREF–/VeREF– = AVSS, Internally Connected