JAJSG80B May   2015  – September 2020 MSP430FG6425 , MSP430FG6426 , MSP430FG6625 , MSP430FG6626

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Type
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 8.7 Thermal Resistance Characteristics
    8. 8.8 Timing and Switching Characteristics
      1. 8.8.1  Power Supply Sequencing
        1. 8.8.1.1 Brownout and Device Reset Power Ramp Requirements
      2. 8.8.2  Reset Timing
        1. 8.8.2.1 Reset Input
      3. 8.8.3  Clock Specifications
        1. 8.8.3.1 Crystal Oscillator, XT1, Low-Frequency Mode
        2. 8.8.3.2 Crystal Oscillator, XT2
        3. 8.8.3.3 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        4. 8.8.3.4 Internal Reference, Low-Frequency Oscillator (REFO)
        5. 8.8.3.5 DCO Frequency
      4. 8.8.4  Wake-up Characteristics
        1. 8.8.4.1 Wake-up Times From Low-Power Modes and Reset
      5. 8.8.5  General-Purpose I/Os
        1. 8.8.5.1 Schmitt-Trigger Inputs – General-Purpose I/O
        2. 8.8.5.2 Inputs – Ports P1, P2, P3, and P4
        3. 8.8.5.3 Leakage Current – General-Purpose I/O
        4. 8.8.5.4 Outputs – General-Purpose I/O (Full Drive Strength)
        5. 8.8.5.5 Outputs – General-Purpose I/O (Reduced Drive Strength)
        6. 8.8.5.6 Output Frequency – Ports P1, P2 and P3
        7. 8.8.5.7 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
        8. 8.8.5.8 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
      6. 8.8.6  PMM
        1. 8.8.6.1 PMM, Core Voltage
        2. 8.8.6.2 PMM, SVS High Side
        3. 8.8.6.3 PMM, SVM High Side
        4. 8.8.6.4 PMM, SVS Low Side
        5. 8.8.6.5 PMM, SVM Low Side
      7. 8.8.7  Timers
        1. 8.8.7.1 Timer_A, Timers TA0, TA1, and TA2
        2. 8.8.7.2 Timer_B, Timer TB0
      8. 8.8.8  Battery Backup
        1. 8.8.8.1 Battery Backup
      9. 8.8.9  USCI
        1. 8.8.9.1 USCI (UART Mode)
        2. 8.8.9.2 USCI (SPI Master Mode)
        3. 8.8.9.3 USCI (SPI Slave Mode)
        4. 8.8.9.4 USCI (I2C Mode)
      10. 8.8.10 LCD Controller
        1. 8.8.10.1 LCD_B Operating Conditions
        2. 8.8.10.2 LCD_B, Electrical Characteristics
      11. 8.8.11 CTSD16
        1. 8.8.11.1 CTSD16, Power Supply and Operating Conditions
        2.       66
        3. 8.8.11.2 CTSD16, External Voltage Reference
        4. 8.8.11.3 CTSD16, Input Range
        5. 8.8.11.4 CTSD16, Performance
        6.       70
        7. 8.8.11.5 Built-in Vcc Sense
        8. 8.8.11.6 Temperature Sensor
      12. 8.8.12 REF
        1. 8.8.12.1 REF and REFBG, Built-In Reference
      13. 8.8.13 DAC
        1. 8.8.13.1 12-Bit DAC, Supply Specifications
        2. 8.8.13.2 12-Bit DAC, Linearity Specifications
        3. 8.8.13.3 12-Bit DAC, Output Specifications
        4. 8.8.13.4 12-Bit DAC, Reference Input Specifications
        5. 8.8.13.5 12-Bit DAC, Dynamic Specifications
        6. 8.8.13.6 12-Bit DAC, Dynamic Specifications (Continued)
      14. 8.8.14 Operational Amplifier
        1. 8.8.14.1 Operational Amplifier, OA0, OA1, PGA Buffers
        2. 8.8.14.2 OA, Current Calculation
      15. 8.8.15 Switches
        1. 8.8.15.1 Ground Switches (GSW0A, GSW0B, GSW1A, GSW1B)
        2. 8.8.15.2 Operational Amplifier Switches
      16. 8.8.16 Comparator
        1. 8.8.16.1 Comparator_B
      17. 8.8.17 USB
        1. 8.8.17.1 Ports PU.0 and PU.1
        2. 8.8.17.2 USB Output Ports DP and DM
        3. 8.8.17.3 USB Input Ports DP and DM
        4. 8.8.17.4 USB-PWR (USB Power System)
        5. 8.8.17.5 USB-PLL (USB Phase-Locked Loop)
      18. 8.8.18 LDO-PWR (LDO Power System)
        1. 8.8.18.1 LDO-PWR (LDO Power System)
      19. 8.8.19 Flash
        1. 8.8.19.1 Flash Memory
      20. 8.8.20 Debug and Emulation
        1. 8.8.20.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Instruction Set
    4. 9.4  Operating Modes
    5. 9.5  Interrupt Vector Addresses
    6. 9.6  USB BSL
    7. 9.7  UART BSL
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  Flash Memory
    10. 9.10 RAM
    11. 9.11 Backup RAM
    12. 9.12 Peripherals
      1. 9.12.1  Digital I/O
      2. 9.12.2  Port Mapping Controller
      3. 9.12.3  Oscillator and System Clock
      4. 9.12.4  Power Management Module (PMM)
      5. 9.12.5  Hardware Multiplier (MPY32)
      6. 9.12.6  Real-Time Clock (RTC_B)
      7. 9.12.7  Watchdog Timer (WDT_A)
      8. 9.12.8  System Module (SYS)
      9. 9.12.9  DMA Controller
      10. 9.12.10 Universal Serial Communication Interface (USCI)
      11. 9.12.11 Timer TA0
      12. 9.12.12 Timer TA1
      13. 9.12.13 Timer TA2
      14. 9.12.14 Timer TB0
      15. 9.12.15 Comparator_B
      16. 9.12.16 Signal Chain
        1. 9.12.16.1 CTSD16
        2. 9.12.16.2 DAC12_A
        3. 9.12.16.3 Operational Amplifiers (OA)
        4. 9.12.16.4 Ground Switches (GSW)
      17. 9.12.17 REF Voltage Reference
      18. 9.12.18 CRC16
      19. 9.12.19 LCD_B
      20. 9.12.20 USB Universal Serial Bus
      21. 9.12.21 LDO and PU Port
      22. 9.12.22 Embedded Emulation Module (EEM) (L Version)
    13. 9.13 Input/Output Diagrams
      1. 9.13.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.13.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.13.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.13.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.13.5  Port P5 (P5.0) Input/Output With Schmitt Trigger
      6. 9.13.6  Port P5 (P5.1 and P5.6) Input/Output With Schmitt Trigger
      7. 9.13.7  Port P5 (P5.3 to P5.5, P5.7) Input/Output With Schmitt Trigger
      8. 9.13.8  Port P6 (P6.0 to P6.1) Input/Output With Schmitt Trigger
      9. 9.13.9  Port P6 (P6.2 and P6.3) Input/Output With Schmitt Trigger
      10. 9.13.10 Port P6 (P6.4) Input/Output With Schmitt Trigger
      11. 9.13.11 Port P6 (P6.5) Input/Output With Schmitt Trigger
      12. 9.13.12 Port P6 (P6.6) Input/Output With Schmitt Trigger
      13. 9.13.13 Port P6 (P6.7) Input/Output With Schmitt Trigger
      14. 9.13.14 Port P7 (P7.2 and P7.3) Input/Output With Schmitt Trigger
      15. 9.13.15 Port P7 (P7.4) Input/Output With Schmitt Trigger
      16. 9.13.16 Port P7 (P7.5) Input/Output With Schmitt Trigger
      17. 9.13.17 Port P7 (P7.6) Input/Output With Schmitt Trigger
      18. 9.13.18 Port P7 (P7.7) Input/Output With Schmitt Trigger
      19. 9.13.19 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      20. 9.13.20 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      21. 9.13.21 Port U (PU.0/DP, PU.1/DM, PUR) USB Ports for MSP430FG662x
      22. 9.13.22 Port J (J.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      23. 9.13.23 Port J (J.1 to J.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 9.14 Device Descriptors
    15. 9.15 Memory
      1. 9.15.1 Peripheral File Map
    16. 9.16 Identification
      1. 9.16.1 Revision Identification
      2. 9.16.2 Device Identification
      3. 9.16.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 CTSD16 Peripheral
        1. 10.2.1.1 Example Measurement Schematic – Differential Input
        2. 10.2.1.2 Example Measurement Schematic – Single-Ended Input
        3. 10.2.1.3 Design Requirements
        4. 10.2.1.4 Detailed Design Procedure
          1. 10.2.1.4.1 OSR and Sampling Frequency
          2. 10.2.1.4.2 Differential Input Range Explanation
          3. 10.2.1.4.3 Single-Ended Input Mode
          4. 10.2.1.4.4 Offset Calibration
        5. 10.2.1.5 Layout Guidelines
      2. 10.2.2 Operational Amplifier With Ground Switches Peripheral
        1. 10.2.2.1 Reference Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
      3. 10.2.3 RTC_B With Battery Backup System
        1. 10.2.3.1 Partial Schematic
        2. 10.2.3.2 Retaining an Accurate Real-Time Clock (RTC) Through Main Supply Interrupts
        3. 10.2.3.3 Charging Super-Capacitors With Built-In Resistive Charger
      4. 10.2.4 LCD_B Peripheral
        1. 10.2.4.1 Partial Schematic
        2. 10.2.4.2 Design Requirements
        3. 10.2.4.3 Detailed Design Procedure
        4. 10.2.4.4 Layout Guidelines
      5. 10.2.5 DAC12 Peripheral
        1. 10.2.5.1 Partial Schematic
        2. 10.2.5.2 Design Requirements
        3. 10.2.5.3 Detailed Design Procedure
        4. 10.2.5.4 Layout Guidelines
      6. 10.2.6 USB Module
      7. 10.2.7 LDO Module
        1. 10.2.7.1 Partial Schematic
  11. 11Device and Documentation Support
    1. 11.1  Getting Started
    2. 11.2  Device Nomenclature
    3. 11.3  Tools and Software
    4. 11.4  Documentation Support
    5. 11.5  Related Links
    6. 11.6  サポート・リソース
    7. 11.7  Trademarks
    8. 11.8  静電気放電に関する注意事項
    9. 11.9  Export Control Notice
    10. 11.10 用語集
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3 Signal Descriptions

Table 7-2 describes the signals for all device variants and package options.

Table 7-2 Signal Descriptions
FUNCTION SIGNAL NAME PIN NO. PIN TYPE(1) DESCRIPTION
PZ ZCA, ZQW
ADC A0 97 B4 I ADC analog single ended input A0
A1 98 B3 I ADC analog single ended input A1
A2 99 A2 I ADC analog single ended input A2
A3 100 D5 I ADC analog single ended input A3
A4 10 E4 I ADC analog single ended input A4
A5 11 E2 I ADC analog single ended input A5
AD0+ 1 A1 I ADC positive analog differential input AD0+
AD0- 2 B2 I ADC negative analog differential input AD0-
AD1+ 3 B1 I ADC positive analog differential input AD1+
AD1- 4 C3 I ADC negative analog differential input AD1-
AD2+ 5 C2 I ADC positive analog differential input AD2+
AD2- 6 C1 I ADC negative analog differential input AD2-
AD3+ 7 D4 I ADC positive analog differential input AD3+
AD3- 8 D2 I ADC negative analog differential input AD3-
VeREF+ 9 D1 I Input for an external reference voltage to the ADC and DAC
BSL BSLRX 36 J6 I BSL receive input
BSLTX 35 M5 O BSL transmit output
Backup VBAK 86 A7 I/O Capacitor for backup subsystem. Do not load this pin externally. For capacitor values, see CBAK in Section 8.3.
VBAT 87 D8 P Backup or secondary supply voltage. If backup voltage is not supplied, connect to DVCC externally.
Charge Pump CPCAP 17 G4 I/O Capacitor for op amp and CTSD16 rail-to-rail charge pump
Clock ACLK 34 L5 O ACLK output (divided by 1, 2, 4, 8, 16, or 32)
RTCCLK 88 D7 O RTCCLK output
SMCLK 46 J8 O SMCLK output
XIN 15 G1 I Input terminal for crystal oscillator XT1
XOUT 14 F1 O Output terminal of crystal oscillator XT1
XT2IN 84 B8 I Input terminal for crystal oscillator XT2
XT2OUT 85 B7 O Output terminal of crystal oscillator XT2
Comparator CB0 97 B4 I Comparator_B input CB0
CB1 98 B3 I Comparator_B input CB1
CB2 99 A2 I Comparator_B input CB2
CB3 100 D5 I Comparator_B input CB3
CB4 1 A1 I Comparator_B input CB4
CB5 2 B2 I Comparator_B input CB5
CB6 3 B1 I Comparator_B input CB6
CB7 4 C3 I Comparator_B input CB7
CB8 5 C2 I Comparator_B input CB8
CB9 6 C1 I Comparator_B input CB9
CB10 7 D4 I Comparator_B input CB10
CB11 8 D2 I Comparator_B input CB11
CBOUT 42 L7 O Comparator_B output
DAC DAC0 10
18		 E4
H2		 O DAC output channel 0
DAC1 11
19		 E2
J1		 O DAC output channel 1
DMA DMAE0 88 D7 I DMA external trigger input
Debug SBWTCK 91 B6 I Spy-Bi-Wire input clock
TCK 95 D6 I Test clock
TCLK 93 A4 I Test clock input
TDI 93 A4 I Test data input
TDO 92 B5 O Test data output
TEST 91 B6 I Test mode pin; selects digital I/O on JTAG pins
TMS 94 E7 I Test mode select
SBWTDIO 96 A3 I/O Spy-Bi-Wire data input/output
GPIO P1.0 34 L5 I/O General-purpose digital I/O with port interrupt
P1.1 35 M5 I/O General-purpose digital I/O with port interrupt
P1.2 36 J6 I/O General-purpose digital I/O with port interrupt
P1.3 37 H6 I/O General-purpose digital I/O with port interrupt
P1.4 38 M6 I/O General-purpose digital I/O with port interrupt
P1.5 39 L6 I/O General-purpose digital I/O with port interrupt
P1.6 40 J7 I/O General-purpose digital I/O with port interrupt
P1.7 41 M7 I/O General-purpose digital I/O with port interrupt
P2.0 18 H2 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.1 19 J1 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.2 20 H4 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.3 21 J2 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.4 22 K1 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.5 23 K2 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.6 24 L2 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P2.7 25 L3 I/O General-purpose digital I/O with port interrupt and mappable secondary function
P3.0 42 L7 I/O General-purpose digital I/O with port interrupt
P3.1 43 H7 I/O General-purpose digital I/O with port interrupt
P3.2 44 M8 I/O General-purpose digital I/O with port interrupt
P3.3 45 L8 I/O General-purpose digital I/O with port interrupt
P3.4 46 J8 I/O General-purpose digital I/O with port interrupt
P3.5 47 M9 I/O General-purpose digital I/O with port interrupt
P3.6 48 L9 I/O General-purpose digital I/O with port interrupt
P3.7 49 M10 I/O General-purpose digital I/O with port interrupt
GPIO P4.0 50 J9 I/O General-purpose digital I/O with port interrupt
P4.1 51 M11 I/O General-purpose digital I/O with port interrupt
P4.2 52 L10 I/O General-purpose digital I/O with port interrupt
P4.3 53 M12 I/O General-purpose digital I/O with port interrupt
P4.4 54 L12 I/O General-purpose digital I/O with port interrupt
P4.5 55 L11 I/O General-purpose digital I/O with port interrupt
P4.6 56 K11 I/O General-purpose digital I/O with port interrupt
P4.7 57 K12 I/O General-purpose digital I/O with port interrupt
P5.0 9 D1 I/O General-purpose digital I/O
P5.1 10 E4 I/O General-purpose digital I/O
P5.3 31 L4 I/O General-purpose digital I/O
P5.4 32 M4 I/O General-purpose digital I/O
P5.5 33 J5 I/O General-purpose digital I/O
P5.6 11 E2 I/O General-purpose digital I/O
P5.7 88 D7 I/O General-purpose digital I/O
P6.0 97 B4 I/O General-purpose digital I/O
P6.1 98 B3 I/O General-purpose digital I/O
P6.2 99 A2 I/O General-purpose digital I/O
P6.3 100 D5 I/O General-purpose digital I/O
P6.4 1 A1 I/O General-purpose digital I/O
P6.5 2 B2 I/O General-purpose digital I/O
P6.6 3 B1 I/O General-purpose digital I/O
P6.7 4 C3 I/O General-purpose digital I/O
P7.2 84 B8 I/O General-purpose digital I/O
P7.3 85 B7 I/O General-purpose digital I/O
P7.4 5 C2 I/O General-purpose digital I/O
P7.5 6 C1 I/O General-purpose digital I/O
P7.6 7 D4 I/O General-purpose digital I/O
P7.7 8 D2 I/O General-purpose digital I/O
P8.0 58 J11 I/O General-purpose digital I/O
P8.1 59 J12 I/O General-purpose digital I/O
P8.2 60 H11 I/O General-purpose digital I/O
P8.3 61 H12 I/O General-purpose digital I/O
P8.4 62 G11 I/O General-purpose digital I/O
P8.5 65 F11 I/O General-purpose digital I/O
P8.6 66 G9 I/O General-purpose digital I/O
P8.7 67 E12 I/O General-purpose digital I/O
GPIO P9.0 68 E11 I/O General-purpose digital I/O
P9.1 69 F9 I/O General-purpose digital I/O
P9.2 70 D12 I/O General-purpose digital I/O
P9.3 71 D11 I/O General-purpose digital I/O
P9.4 72 E9 I/O General-purpose digital I/O
P9.5 73 C12 I/O General-purpose digital I/O
P9.6 74 C11 I/O General-purpose digital I/O
P9.7 75 D9 I/O General-purpose digital I/O
PJ.0 92 B5 I/O General-purpose digital I/O
PJ.1 93 A4 I/O General-purpose digital I/O
PJ.2 94 E7 I/O General-purpose digital I/O
PJ.3 95 D6 I/O General-purpose digital I/O
PU.0 77 A12 I/O General-purpose digital I/O - controlled by USB control register (FG662x devices) or PU control register
PU.1 79 A11 I/O General-purpose digital I/O - controlled by USB control register (FG662x devices) or PU control register
Ground Switch G0SW0 3 B1 I Analog switch to AVSS. Internally connected to ADC positive analog differential input AD1+.
G0SW1 4 C3 I Analog switch to AVSS. Internally connected to ADC negative analog differential input AD1-.
G1SW0 7 D4 I Analog switch to AVSS. Internally connected to ADC positive analog differential input AD3+.
G1SW1 8 D2 I Analog switch to AVSS. Internally connected to ADC negative analog differential input AD3-.
I2C UCB1SCL 66 G9 I/O USCI_B1 I2C clock
UCB1SDA 65 F11 I/O USCI_B1 I2C data
LCD COM0 30 J4 O LCD common output COM0 for LCD backplane
COM1 31 L4 O LCD common output COM1 for LCD backplane
COM2 32 M4 O LCD common output COM2 for LCD backplane
COM3 33 J5 I/O LCD common output COM3 for LCD backplane
LCDCAP 29 M3 I/O LCD capacitor connection
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
LCDREF 24 L2 I External reference voltage input for regulated LCD voltage
R03 22 K1 I/O Input/output port of lowest analog LCD voltage (V5)
R13 24 L2 I/O Input/output port of third most positive analog LCD voltage (V3 or V4)
R23 25 L3 I/O Input/output port of second most positive analog LCD voltage (V2)
R33 29 M3 I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
S0 75 D9 O LCD segment output S0
S1 74 C11 O LCD segment output S1
S2 73 C12 O LCD segment output S2
S3 72 E9 O LCD segment output S3
S4 71 D11 O LCD segment output S4
S5 70 D12 O LCD segment output S5
S6 69 F9 O LCD segment output S6
LCD S7 68 E11 O LCD segment output S7
S8 67 E12 O LCD segment output S8
S9 66 G9 O LCD segment output S9
S10 65 F11 O LCD segment output S10
S11 62 G11 O LCD segment output S11
S12 61 H12 O LCD segment output S12
S13 60 H11 O LCD segment output S13
S14 59 J12 O LCD segment output S14
S15 58 J11 O LCD segment output S15
S16 57 K12 O LCD segment output S16
S17 56 K11 O LCD segment output S17
S18 55 L11 O LCD segment output S18
S19 54 L12 O LCD segment output S19
S20 53 M12 O LCD segment output S20
S21 52 L10 O LCD segment output S21
S22 51 M11 O LCD segment output S22
S23 50 J9 O LCD segment output S23
S24 49 M10 O LCD segment output S24
S25 48 L9 O LCD segment output S25
S26 47 M9 O LCD segment output S26
S27 46 J8 O LCD segment output S27
S28 45 L8 O LCD segment output S28
S29 44 M8 O LCD segment output S29
S30 43 H7 O LCD segment output S30
S31 42 L7 O LCD segment output S31
S32 41 M7 O LCD segment output S32
S33 40 J7 O LCD segment output S33
S34 39 L6 O LCD segment output S34
S35 38 M6 O LCD segment output S35
S36 37 H6 O LCD segment output S36
S37 36 J6 O LCD segment output S37
S38 35 M5 O LCD segment output S38
S39 34 L5 O LCD segment output S39
S40 33 J5 O LCD segment output S40
S41 32 M4 O LCD segment output S41
S42 31 L4 O LCD segment output S42
Mappable P2MAP0 18 H2 I/O Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output
Mapping Options: See Table 9-8
P2MAP1 19 J1 I/O Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data
Mapping Options: See Table 9-8
P2MAP2 20 H4 I/O Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock
Mapping Options: See Table 9-8
P2MAP3 21 J2 I/O Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
Mapping Options: See Table 9-8
P2MAP4 22 K1 I/O Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out
Mapping Options: See Table 9-8
P2MAP5 23 K2 I/O Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in
Mapping Options: See Table 9-8
P2MAP6 24 L2 I/O Default mapping: no secondary function
Mapping Options: See Table 9-8
P2MAP7 25 L3 I/O Default mapping: no secondary function
Mapping Options: See Table 9-8
Noise Reduction NR 12 E1 I Noise reduction. Connect pin to analog ground.
Op Amp OA1IN0 6 C1 I OA1 negative input internally connected to ADC negative analog differential input AD2-
OA0IN0 2 B2 I OA0 negative input internally connected to ADC negative analog differential input AD0-
OA0IP0 99 A2 I OA0 positive input internally connected to ADC analog input A2
OA0O 1 A1 O OA0 output internally connected to ADC positive analog differential input AD0+
OA1IP0 100 D5 I OA1 positive input internally connected to ADC analog input A3
OA1O 5 C2 O OA1 output internally connected to ADC positive analog differential input AD2+
Power AVSS1 13 F2 P Analog ground supply
AVSS2 83 A8 P Analog ground supply
AVCC 16 H1, G2 P Analog power supply
DVCC1 26 L1 P Digital power supply
DVCC2 64 F12 P Digital power supply
DVCC3 89 A6 P Digital power supply
DVSS1 27 M1 P Digital ground supply
DVSS2 63 G12 P Digital ground supply
DVSS3 90 A5 P Digital ground supply
LDOI 80 A10 I LDO input (not available on FG662x devices)
LDOO 81 A9 O LDO output (not available on FG662x devices)
VCORE(2) 28 M2 O Regulated core power supply (internal use only, no external current loading)
REF VREFBG 9 D1 O Output of reference voltage to the ADC and DAC
Reserved NC 78
82		 B10
B9		 I/O Not connected (not available on FG662x devices)
Reserved – E5, E6, E8, F4, F5, F8, G5, G8, H5, H8, H9 – Reserved. Internally connected to DVSS. TI recommends external connection to ground (DVSS).
SPI UCA1CLK 59 J12 I/O USCI_A1 clock input/output
UCA1SIMO 60 H11 I/O USCI_A1 SPI slave in/master out
UCA1SOMI 61 H12 I/O USCI_A1 SPI slave out/master in
UCA1STE 62 G11 I/O USCI_A1 SPI slave transmit enable
UCB1CLK 62 G11 I/O USCI_B1 clock input/output
UCB1SIMO 65 F11 I/O USCI_B1 SPI slave in/master out
UCB1SOMI 66 G9 I/O USCI_B1 SPI slave out/master in
UCB1STE 59 J12 I/O USCI_B1 SPI slave transmit enable
System NMI 96 A3 I Nonmaskable interrupt input
RST 96 A3 I/O Reset input (active low)(3)
SVMOUT 57 K12 O SVM output
Timer_A TA0.0 35 M5 I/O Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
TA0.1 36 J6 I/O Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
40 J7 I/O Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output
TA0.2 37 H6 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output
41 M7 I/O Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output
TA0.3 38 M6 I/O Timer TA0 CCR3 capture: CCI3A input compare: Out3 output
TA0.4 39 L6 I/O Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output
TA0CLK 34 L5 I Timer TA0 clock signal TACLK input
TA1.0 43 H7 I/O Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
TA1.1 44 M8 I/O Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
TA1.2 45 L8 I/O Timer TA1 capture CCR2: CCI2A input, compare: Out2 output
TA1CLK 42 L7 I Timer TA1 clock input
TA2.0 47 M9 I/O Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
TA2.1 48 L9 I/O Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
TA2.2 49 M10 I/O Timer TA2 capture CCR2: CCI2A input, compare: Out2 output
TA2CLK 46 J8 I Timer TA2 clock input
Timer_B TB0.0 50 J9 I/O Timer TB0 capture CCR0: CCI0A input, compare: Out0 output
TB0.1 51 M11 I/O Timer TB0 capture CCR1: CCI1A input, compare: Out1 output
TB0.2 52 L10 I/O Timer TB0 capture CCR2: CCI2A input, compare: Out2 output
TB0.3 53 M12 I/O Timer TB0 capture CCR3: CCI3A input, compare: Out3 output
TB0.4 54 L12 I/O Timer TB0 capture CCR4: CCI4A input, compare: Out4 output
TB0.5 55 L11 I/O Timer TB0 capture CCR5: CCI5A input, compare: Out5 output
TB0.6 56 K11 I/O Timer TB0 capture CCR6: CCI6A input, compare: Out6 output
TB0CLK 58 J11 I Timer TB0 clock input
TB0OUTH 57 K12 I Timer TB0: switch all PWM outputs to high impedance
UART UCA1CLK 59 J12 I/O USCI_A1 clock input/output
UCA1RXD 61 H12 I USCI_A1 UART receive data
UCA1TXD 60 H11 O USCI_A1 UART transmit data
USB (FG662x only) DM 79 A11 I/O USB data terminal DM (not available on FG6426 and FG6425 devices)
DP 77 A12 I/O USB data terminal DP (not available on FG6426 and FG6425 devices)
PUR 78 B10 I/O USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to invoke the default USB BSL.

Recommended 1-MΩ resistor to ground. See Section 9.6 for more information.

Not available on FG6426 and FG6425 devices.
V18 82 B9 O USB regulated power (internal use only, no external current loading) (not available on FG6426 and FG6425 devices)
VBUS 80 A10 I USB LDO input (connect to USB power source) (not available on FG6426 and FG6425 devices)
VSSU 76 B11
B12		 P USB PHY ground supply
VUSB 81 A9 O USB LDO output (not available on FG6426 and FG6425 devices)
(1) I = input, O = output, I/O = input or output, P = power
(2) VCORE is for internal use only. No external current loading is possible. VCORE must be connected to the recommended capacitor value, CVCORE.
(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.