JAJSCD6E August   2016  – June 2021 MSP430FR2000 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Connection of Unused Pins
    6. 7.6 Buffer Type
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics – LPM Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Resistance Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 DCO Frequency
        4. 8.12.3.4 REFO
        5. 8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. 8.12.3.6 Module Oscillator (MODOSC)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Digital I/O Typical Characteristics
      5. 8.12.5  VREF+ Built-in Reference
        1. 8.12.5.1 VREF+ Characteristics
      6. 8.12.6  Timer_B
        1. 8.12.6.1 Timer_B
      7. 8.12.7  eUSCI
        1. 8.12.7.1 eUSCI (UART Mode) Clock Frequency
        2. 8.12.7.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.12.7.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.12.7.5 eUSCI (SPI Slave Mode) Switching Characteristics
      8. 8.12.8  ADC
        1. 8.12.8.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.8.2 ADC, 10-Bit Timing Parameters
        3. 8.12.8.3 ADC, 10-Bit Linearity Parameters
      9. 8.12.9  Enhanced Comparator (eCOMP)
        1. 8.12.9.1 eCOMP Characteristics
      10. 8.12.10 FRAM
        1. 8.12.10.1 FRAM Characteristics
      11. 8.12.11 Emulation and Debug
        1. 8.12.11.1 JTAG, Spy-Bi-Wire Interface
        2. 8.12.11.2 JTAG, 4-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Memory Organization
    6. 9.6  Bootloader (BSL)
    7. 9.7  JTAG Standard Interface
    8. 9.8  Spy-Bi-Wire Interface (SBW)
    9. 9.9  FRAM
    10. 9.10 Memory Protection
    11. 9.11 Peripherals
      1. 9.11.1  Power-Management Module (PMM) and On-Chip Reference Voltages
      2. 9.11.2  Clock System (CS) and Clock Distribution
      3. 9.11.3  General-Purpose Input/Output Port (I/O)
      4. 9.11.4  Watchdog Timer (WDT)
      5. 9.11.5  System Module (SYS)
      6. 9.11.6  Cyclic Redundancy Check (CRC)
      7. 9.11.7  Enhanced Universal Serial Communication Interface (eUSCI_A0)
      8. 9.11.8  Timers (Timer0_B3)
      9. 9.11.9  Backup Memory (BAKMEM)
      10. 9.11.10 Real-Time Clock (RTC) Counter
      11. 9.11.11 10-Bit Analog-to-Digital Converter (ADC)
      12. 9.11.12 eCOMP0
      13. 9.11.13 Embedded Emulation Module (EEM)
      14. 9.11.14 Peripheral File Map
      15. 9.11.15 Input/Output Diagrams
        1. 9.11.15.1 Port P1 Input/Output With Schmitt Trigger
        2. 9.11.15.2 Port P2 Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptors (TLV)
    13. 9.13 Identification
      1. 9.13.1 Revision Identification
      2. 9.13.2 Device Identification
      3. 9.13.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
    3. 10.3 Typical Applications
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3 Signal Descriptions

#GUID-05260FF3-2DB6-49C5-B8C1-A7DDB2C43CAF/SLAS9424668 describes the signals for all device variants and package options.

Table 7-2 Signal Descriptions
FUNCTIONSIGNAL NAMEPIN NUMBERPIN TYPEDESCRIPTION
PW16RLL
ADC(1)A0220IAnalog input A0
A1123IAnalog input A1
A21619IAnalog input A2
A31517IAnalog input A3
A41416IAnalog input A4
A51315IAnalog input A5
A61214IAnalog input A6
A71113IAnalog input A7
Veref+220IADC positive reference
Veref-1619IADC negative reference
eCOMP0C0220IComparator input channel C0
C1123IComparator input channel C1
C21619IComparator input channel C2
C31517IComparator input channel C3
COUT108OComparator output channel COUT
ClockACLK123OACLK output
MCLK87OMCLK output
SMCLK220OSMCLK output
XIN75IInput terminal for crystal oscillator
XOUT87OOutput terminal for crystal oscillator
DebugSBWTCK31ISpy-Bi-Wire input clock
SBWTDIO42I/OSpy-Bi-Wire data input/output
TCK1416ITest clock
TCLK1214ITest clock input
TDI1214ITest data input
TDO1113OTest data output
TMS1315ITest mode select
TEST31ITest mode pin – selected digital I/O on JTAG pins
SystemNMI42INonmaskable interrupt input
RST42I/OReset input, active low
PowerDVCC53PPower supply
DVSS64PPower ground
VREF+1113POutput of positive reference voltage with ground as reference
GPIOP1.0220I/OGeneral-purpose I/O
P1.1123I/OGeneral-purpose I/O
P1.21619I/OGeneral-purpose I/O
P1.31517I/OGeneral-purpose I/O
P1.41416I/OGeneral-purpose I/O (2)
P1.51315I/OGeneral-purpose I/O (2)
P1.61214I/OGeneral-purpose I/O(2)
P1.71113I/OGeneral-purpose I/O(2)
P2.0108I/OGeneral-purpose I/O
P2.1911I/OGeneral-purpose I/O
P2.687I/OGeneral-purpose I/O
P2.775I/OGeneral-purpose I/O
SPI and UARTUCA0CLK1315I/OeUSCI_A0 SPI clock input/output
UCA0RXD1214IeUSCI_A0 UART receive data
UCA0SIMO1113I/OeUSCI_A0 SPI slave in/master out
UCA0SOMI1214I/OeUSCI_A0 SPI slave out/master in
UCA0STE1416I/OeUSCI_A0 SPI slave transmit enable
UCA0TXD1113OeUSCI_A0 UART transmit data
UCA0CLK(4)123I/OeUSCI_A0 SPI clock input/output
UCA0RXD(4)1619IeUSCI_A0 UART receive data
UCA0SIMO(4)1517I/OeUSCI_A0 SPI slave in/master out
UCA0SOMI(4)1619I/OeUSCI_A0 SPI slave out/master in
UCA0STE(4)220I/OeUSCI_A0 SPI slave transmit enable
UCA0TXD(4)1517OeUSCI_A0 UART transmit data
Timer_BTB0.11214I/OTimer TB0 CCR1 capture: CCI1A input, compare: Out1 outputs
TB0.21113I/OTimer TB0 CCR2 capture: CCI2A input, compare: Out2 outputs
TB0CLK75ITimer clock input TBCLK for TB0
TB0TRG1619ITB0 external trigger input for TB0OUTH
TB0.1(3)108I/OTimer TB0 CCR1 capture: CCI1A input, compare: Out1 outputs
TB0.2(3)911I/OTimer TB0 CCR2 capture: CCI2A input, compare: Out2 outputs
NC padNC–6, 9, 10, 12, 18, 21, 22, 24–Do not connect
VQFN padPad–PadVQFN package (RLL) exposed thermal pad. Connect to VSS.
(1) The ADC is not available on the MSP430FR2000 device.
(2) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to prevent collisions.
(3) This is the remapped functionality controlled by the TBRMP bit in the SYSCFG3 register. Only one selected port is valid at the same time when TB0 acts as capture input functionality. TB0 PWM outputs regardless of the setting on this remap bit.
(4) This is the remapped functionality controlled by the USCIARMP bit in the SYSCFG3 register. Only one selected port is valid at the same time.