JAJSCD6E August 2016 – June 2021 MSP430FR2000 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111
PRODUCTION DATA
#GUID-2BB747CA-D959-4555-859B-6E05603B0910/SLASE782520 lists the base address and the memory size of the registers for each peripheral.
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
SFR interrupt enable | SFRIE1 | 00h |
SFR interrupt flag | SFRIFG1 | 02h |
SFR reset pin control | SFRRPCR | 04h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
PMM control 0 | PMMCTL0 | 00h |
PMM control 1 | PMMCTL1 | 02h |
PMM control 2 | PMMCTL2 | 04h |
PMM interrupt flags | PMMIFG | 0Ah |
PM5 control 0 | PM5CTL0 | 10h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
System control | SYSCTL | 00h |
Bootloader configuration area | SYSBSLC | 02h |
JTAG mailbox control | SYSJMBC | 06h |
JTAG mailbox input 0 | SYSJMBI0 | 08h |
JTAG mailbox input 1 | SYSJMBI1 | 0Ah |
JTAG mailbox output 0 | SYSJMBO0 | 0Ch |
JTAG mailbox output 1 | SYSJMBO1 | 0Eh |
User NMI vector generator | SYSUNIV | 1Ah |
System NMI vector generator | SYSSNIV | 1Ch |
Reset vector generator | SYSRSTIV | 1Eh |
System configuration 0 | SYSCFG0 | 20h |
System configuration 1 | SYSCFG1 | 22h |
System configuration 2 | SYSCFG2 | 24h |
System configuration 3 | SYSCFG3 | 26h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
CS control 0 | CSCTL0 | 00h |
CS control 1 | CSCTL1 | 02h |
CS control 2 | CSCTL2 | 04h |
CS control 3 | CSCTL3 | 06h |
CS control 4 | CSCTL4 | 08h |
CS control 5 | CSCTL5 | 0Ah |
CS control 6 | CSCTL6 | 0Ch |
CS control 7 | CSCTL7 | 0Eh |
CS control 8 | CSCTL8 | 10h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
FRAM control 0 | FRCTL0 | 00h |
General control 0 | GCCTL0 | 04h |
General control 1 | GCCTL1 | 06h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
CRC data input | CRC16DI | 00h |
CRC data input reverse byte | CRCDIRB | 02h |
CRC initialization and result | CRCINIRES | 04h |
CRC result reverse byte | CRCRESR | 06h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
Watchdog timer control | WDTCTL | 00h |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
Port P1 input | P1IN | 00h |
Port P1 output | P1OUT | 02h |
Port P1 direction | P1DIR | 04h |
Port P1 pulling enable | P1REN | 06h |
Port P1 selection 0 | P1SEL0 | 0Ah |
Port P1 selection 1 | P1SEL1 | 0Ch |
Port P1 interrupt vector word | P1IV | 0Eh |
Port P1 complement selection | P1SELC | 16h |
Port P1 interrupt edge select | P1IES | 18h |
Port P1 interrupt enable | P1IE | 1Ah |
Port P1 interrupt flag | P1IFG | 1Ch |
Port P2 input | P2IN | 01h |
Port P2 output | P2OUT | 03h |
Port P2 direction | P2DIR | 05h |
Port P2 pulling enable | P2REN | 07h |
Port P2 selection 0 | P2SEL0 | 0Bh |
Port P2 selection 1 | P2SEL1 | 0Dh |
Port P2 complement selection | P2SELC | 17h |
Port P2 interrupt vector word | P2IV | 1Eh |
Port P2 interrupt edge select | P2IES | 19h |
Port P2 interrupt enable | P2IE | 1Bh |
Port P2 interrupt flag | P2IFG | 1Dh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
Capacitive Touch I/O 0 control | CAPIO0CTL | 0Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
RTC control | RTCCTL | 00h |
RTC interrupt vector | RTCIV | 04h |
RTC modulo | RTCMOD | 08h |
RTC counter | RTCCNT | 0Ch |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
TB0 control | TB0CTL | 00h |
Capture/compare control 0 | TB0CCTL0 | 02h |
Capture/compare control 1 | TB0CCTL1 | 04h |
Capture/compare control 2 | TB0CCTL2 | 06h |
TB0 counter | TB0R | 10h |
Capture/compare 0 | TB0CCR0 | 12h |
Capture/compare 1 | TB0CCR1 | 14h |
Capture/compare 2 | TB0CCR2 | 16h |
TB0 expansion 0 | TB0EX0 | 20h |
TB0 interrupt vector | TB0IV | 2Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
eUSCI_A control word 0 | UCA0CTLW0 | 00h |
eUSCI_A control word 1 | UCA0CTLW1 | 02h |
eUSCI_A control rate 0 | UCA0BR0 | 06h |
eUSCI_A control rate 1 | UCA0BR1 | 07h |
eUSCI_A modulation control | UCA0MCTLW | 08h |
eUSCI_A status | UCA0STAT | 0Ah |
eUSCI_A receive buffer | UCA0RXBUF | 0Ch |
eUSCI_A transmit buffer | UCA0TXBUF | 0Eh |
eUSCI_A LIN control | UCA0ABCTL | 10h |
eUSCI_A IrDA transmit control | lUCA0IRTCTL | 12h |
eUSCI_A IrDA receive control | IUCA0IRRCTL | 13h |
eUSCI_A interrupt enable | UCA0IE | 1Ah |
eUSCI_A interrupt flags | UCA0IFG | 1Ch |
eUSCI_A interrupt vector word | UCA0IV | 1Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
Backup memory 0 | BAKMEM0 | 00h |
Backup memory 1 | BAKMEM1 | 02h |
Backup memory 2 | BAKMEM2 | 04h |
Backup memory 3 | BAKMEM3 | 06h |
Backup memory 4 | BAKMEM4 | 08h |
Backup memory 5 | BAKMEM5 | 0Ah |
Backup memory 6 | BAKMEM6 | 0Ch |
Backup memory 7 | BAKMEM7 | 0Eh |
Backup memory 8 | BAKMEM8 | 10h |
Backup memory 9 | BAKMEM9 | 12h |
Backup memory 10 | BAKMEM10 | 14h |
Backup memory 11 | BAKMEM11 | 16h |
Backup memory 12 | BAKMEM12 | 18h |
Backup memory 13 | BAKMEM13 | 1Ah |
Backup memory 14 | BAKMEM14 | 1Ch |
Backup memory 15 | BAKMEM15 | 1Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
ADC control 0 | ADCCTL0 | 00h |
ADC control 1 | ADCCTL1 | 02h |
ADC control 2 | ADCCTL2 | 04h |
ADC window comparator low threshold | ADCLO | 06h |
ADC window comparator high threshold | ADCHI | 08h |
ADC memory control 0 | ADCMCTL0 | 0Ah |
ADC conversion memory | ADCMEM0 | 12h |
ADC interrupt enable | ADCIE | 1Ah |
ADC interrupt flags | ADCIFG | 1Ch |
ADC interrupt vector word | ADCIV | 1Eh |
REGISTER DESCRIPTION | REGISTER | OFFSET |
---|---|---|
Comparator control 0 | CPCTL0 | 00h |
Comparator control 1 | CPCTL1 | 02h |
Comparator interrupt | CPINT | 06h |
Comparator interrupt vector | CPIV | 08h |
Comparator built-in DAC control | CPDACCTL | 10h |
Comparator built-in DAC data | CPDACDATA | 12h |