JAJSCD6E August   2016  – June 2021 MSP430FR2000 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Connection of Unused Pins
    6. 7.6 Buffer Type
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics – LPM Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Resistance Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 DCO Frequency
        4. 8.12.3.4 REFO
        5. 8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. 8.12.3.6 Module Oscillator (MODOSC)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Digital I/O Typical Characteristics
      5. 8.12.5  VREF+ Built-in Reference
        1. 8.12.5.1 VREF+ Characteristics
      6. 8.12.6  Timer_B
        1. 8.12.6.1 Timer_B
      7. 8.12.7  eUSCI
        1. 8.12.7.1 eUSCI (UART Mode) Clock Frequency
        2. 8.12.7.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.12.7.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.12.7.5 eUSCI (SPI Slave Mode) Switching Characteristics
      8. 8.12.8  ADC
        1. 8.12.8.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.8.2 ADC, 10-Bit Timing Parameters
        3. 8.12.8.3 ADC, 10-Bit Linearity Parameters
      9. 8.12.9  Enhanced Comparator (eCOMP)
        1. 8.12.9.1 eCOMP Characteristics
      10. 8.12.10 FRAM
        1. 8.12.10.1 FRAM Characteristics
      11. 8.12.11 Emulation and Debug
        1. 8.12.11.1 JTAG, Spy-Bi-Wire Interface
        2. 8.12.11.2 JTAG, 4-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Memory Organization
    6. 9.6  Bootloader (BSL)
    7. 9.7  JTAG Standard Interface
    8. 9.8  Spy-Bi-Wire Interface (SBW)
    9. 9.9  FRAM
    10. 9.10 Memory Protection
    11. 9.11 Peripherals
      1. 9.11.1  Power-Management Module (PMM) and On-Chip Reference Voltages
      2. 9.11.2  Clock System (CS) and Clock Distribution
      3. 9.11.3  General-Purpose Input/Output Port (I/O)
      4. 9.11.4  Watchdog Timer (WDT)
      5. 9.11.5  System Module (SYS)
      6. 9.11.6  Cyclic Redundancy Check (CRC)
      7. 9.11.7  Enhanced Universal Serial Communication Interface (eUSCI_A0)
      8. 9.11.8  Timers (Timer0_B3)
      9. 9.11.9  Backup Memory (BAKMEM)
      10. 9.11.10 Real-Time Clock (RTC) Counter
      11. 9.11.11 10-Bit Analog-to-Digital Converter (ADC)
      12. 9.11.12 eCOMP0
      13. 9.11.13 Embedded Emulation Module (EEM)
      14. 9.11.14 Peripheral File Map
      15. 9.11.15 Input/Output Diagrams
        1. 9.11.15.1 Port P1 Input/Output With Schmitt Trigger
        2. 9.11.15.2 Port P2 Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptors (TLV)
    13. 9.13 Identification
      1. 9.13.1 Revision Identification
      2. 9.13.2 Device Identification
      3. 9.13.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
    3. 10.3 Typical Applications
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.12.9.1 eCOMP Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC Supply voltage 2.0 3.6 V
VIC Common-mode input range 0 VCC V
VHYS DC input hysteresis CPEN = 1, CPHSEL = 00 2.0 V to 3.6 V 0 mV
CPEN = 1, CPHSEL = 01 10
CPEN = 1, CPHSEL = 10 20
CPEN = 1, CPHSEL = 11 30
VOFFSET Input offset voltage CPEN = 1, CPMSEL = 0, CPHSEL = 00 2.0 V to 3.6 V -40 ±5 +40 mV
CPEN = 1, CPMSEL = 1, CPHSEL = 00 ±10
ICOMP Quiescent current draw from VCC, only comparator VIC = VCC/2, CPEN = 1, CPMSEL = 0 2.0 V to 3.6 V 22 35 µA
VIC = VCC/2, CPEN = 1, CPMSEL = 1 1.3 3.5
IDAC Quiescent current draw from VCC, only DAC CPDACREFS = 0, CPEN = 0 2.0 V to 3.6 V 0.5 µA
CIN Input channel capacitance#SLASE588826 2.0 V to 3.6 V 1 pF
RIN Input channel series resistance On (switch closed) 2.0 V to 3.6 V 10 20 kΩ
Off (switch open) 50 MΩ
tPD Propagation delay, response time CPMSEL = 0, CPFLT = 0,
Overdrive = 20 mV#SLASE788769		 2.0 V to 3.6 V 1 µs
CPMSEL = 1, CPFLT = 0,
Overdrive = 20 mV#SLASE788769		 2.4
tEN_CP Comparator enable time CPEN = 0→1, CPMSEL = 0,
V+ and V- from pads, Overdrive = 20 mV#SLASE788769		 2.0 V to 3.6 V 9.3 µs
CPEN = 0→1, CPMSEL = 1,
V+ and V- from pads, Overdrive = 20 mV#SLASE788769		 12
tEN_CP_DAC Comparator with reference DAC enable time CPEN = 0→1, CPDACEN=0→1,
CPMSEL = 0, CPDACREFS = 1,
CPDACBUF1 = 0F, Overdrive = 20 mV#SLASE788769		 2.0 V to 3.6 V 9.3 µs
CPEN = 0→1, CPDACEN=0→1,
CPMSEL = 1, CPDACREFS = 1,
CPDACBUF1 = 0F, Overdrive = 20 mV #SLASE788769		 113
tFDLY Propagation delay with analog filter active CPMSEL = 0, CPFLTDY = 00,
Overdrive = 20 mV,#SLASE788769
CPFLT = 1		 2.0 V to 3.6 V 0.7 µs
CPMSEL = 0, CPFLTDY = 01,
Overdrive = 20 mV,#SLASE788769
CPFLT = 1		 1.1
CPMSEL = 0, CPFLTDY = 10,
Overdrive = 20 mV,#SLASE788769 CPFLT = 1		 1.9
CPMSEL = 0, CPFLTDY = 11,
Overdrive = 20 mV,#SLASE788769 CPFLT = 1		 3.7
VCP_DAC Reference voltage for built-in 6-bit DAC VIN = reference into 6-bit DAC,
DAC uses internal REF, n = 0 to 63		 2.0 V to 3.6 V VIN × n / 64 V
VIN = reference into 6-bit DAC,
DAC uses VCC as REF, n = 0 to 63		 VIN × n / 64
INL Integral nonlinearity 2.0 V to 3.6 V –0.5 +0.5 LSB
DNL Differential nonlinearity 2.0 V to 3.6 V –0.5 +0.5 LSB
Zero scale 2.0 V to 3.6 V 0 LSB
IDACOFF Leakage current 2.0 V to 3.6 V 5 nA
(1) For the eCOMP CIN model, see #SLASE582649.
(2) This is measured over the input offset.
GUID-5D1DD470-CC38-4CC1-96E0-6DEE50A763C7-low.gif Figure 8-14 eCOMP Input Circuit