JAJSCD6E August   2016  – June 2021 MSP430FR2000 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Connection of Unused Pins
    6. 7.6 Buffer Type
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics – LPM Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Resistance Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 DCO Frequency
        4. 8.12.3.4 REFO
        5. 8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. 8.12.3.6 Module Oscillator (MODOSC)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Digital I/O Typical Characteristics
      5. 8.12.5  VREF+ Built-in Reference
        1. 8.12.5.1 VREF+ Characteristics
      6. 8.12.6  Timer_B
        1. 8.12.6.1 Timer_B
      7. 8.12.7  eUSCI
        1. 8.12.7.1 eUSCI (UART Mode) Clock Frequency
        2. 8.12.7.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.12.7.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.12.7.5 eUSCI (SPI Slave Mode) Switching Characteristics
      8. 8.12.8  ADC
        1. 8.12.8.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.8.2 ADC, 10-Bit Timing Parameters
        3. 8.12.8.3 ADC, 10-Bit Linearity Parameters
      9. 8.12.9  Enhanced Comparator (eCOMP)
        1. 8.12.9.1 eCOMP Characteristics
      10. 8.12.10 FRAM
        1. 8.12.10.1 FRAM Characteristics
      11. 8.12.11 Emulation and Debug
        1. 8.12.11.1 JTAG, Spy-Bi-Wire Interface
        2. 8.12.11.2 JTAG, 4-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Memory Organization
    6. 9.6  Bootloader (BSL)
    7. 9.7  JTAG Standard Interface
    8. 9.8  Spy-Bi-Wire Interface (SBW)
    9. 9.9  FRAM
    10. 9.10 Memory Protection
    11. 9.11 Peripherals
      1. 9.11.1  Power-Management Module (PMM) and On-Chip Reference Voltages
      2. 9.11.2  Clock System (CS) and Clock Distribution
      3. 9.11.3  General-Purpose Input/Output Port (I/O)
      4. 9.11.4  Watchdog Timer (WDT)
      5. 9.11.5  System Module (SYS)
      6. 9.11.6  Cyclic Redundancy Check (CRC)
      7. 9.11.7  Enhanced Universal Serial Communication Interface (eUSCI_A0)
      8. 9.11.8  Timers (Timer0_B3)
      9. 9.11.9  Backup Memory (BAKMEM)
      10. 9.11.10 Real-Time Clock (RTC) Counter
      11. 9.11.11 10-Bit Analog-to-Digital Converter (ADC)
      12. 9.11.12 eCOMP0
      13. 9.11.13 Embedded Emulation Module (EEM)
      14. 9.11.14 Peripheral File Map
      15. 9.11.15 Input/Output Diagrams
        1. 9.11.15.1 Port P1 Input/Output With Schmitt Trigger
        2. 9.11.15.2 Port P2 Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptors (TLV)
    13. 9.13 Identification
      1. 9.13.1 Revision Identification
      2. 9.13.2 Device Identification
      3. 9.13.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
    3. 10.3 Typical Applications
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.11.15.1 Port P1 Input/Output With Schmitt Trigger

#SLASE781011 shows the port diagram. Table 9-34 summarizes the selection of the pin functions.

GUID-933A134B-C4A7-4DB1-B45D-C25A7D68DFAF-low.gif
Functional representation only.
The ADC (signals A0 to A7, Veref+, and Veref-) is not available on the MSP430FR2000 device.
Figure 9-1 Port P1 Input/Output With Schmitt Trigger
Table 9-34 Port P1 Pin Functions
PIN NAME (P1.x) x FUNCTION CONTROL BITS AND SIGNALS#SLASE788811
P1DIR.x P1SELx JTAG
P1.0/UCA0STE/SMCLK/ C0/A0/Veref+ 0 P1.0 (I/O) I: 0; O: 1 00 N/A
UCA0STE X 01 N/A
SMCLK 1 10 N/A
VSS 0
C0, A0/Veref+#TG425091478 X 11 N/A
P1.1/UCA0CLK/ACLK/ C1/A1 1 P1.1 (I/O) I: 0; O: 1 0 N/A
UCA0CLK X 01 N/A
ACLK 1 10 N/A
VSS 0
C1, A1#TG425091478 X 11 N/A
P1.2/UCA0RXD/ UCA0SOMI/TB0TRG/ C2/A2/Veref- 2 P1.2 (I/O) I: 0; O: 1 00 N/A
UCA0RXD/UCA0SOMI X 01 N/A
TB0TRG 0 10 N/A
C2, A2/Veref-#TG425091478 X 11 N/A
P1.3/UCA0TXD/ UCA0SIMO/C3/A3 3 P1.3 (I/O) I: 0; O: 1 00 N/A
UCA0TXD/UCA0SIMO X 01 N/A
C3, A3#TG425091478 X 11 N/A
P1.4/UCA0STE/TCK/A4 4 P1.4 (I/O) I: 0; O: 1 00 Disabled
UCA0STE X 01 N/A
A4#TG425091478 X 11 Disabled
JTAG TCK X X TCK
P1.5/UCA0CLK/TMS/A5 5 P1.5 (I/O) I: 0; O: 1 00 Disabled
UCA0CLK X 01 N/A
A5#TG425091478 X 11 Disabled
JTAG TMS X X TMS
P1.6/UCA0RXD/ UCA0SOMI/TB0.1/ TDI/TCLK/A6 6 P1.6 (I/O) I: 0; O: 1 00 Disabled
UCA0RXD/UCA0SOMI X 01 N/A
TB0.CCI1A 0 10 N/A
TB0.1 1
A6#TG425091478 X 11 Disabled
JTAG TDI/TCLK X X TDI/TCLK
P1.7/UCA0TXD/ UCA0SIMO/TB0.2/ TDO/A7/VREF+ 7 P1.7 (I/O) I: 0; O: 1 00 Disabled
UCA0TXD/UCA0SIMO X 01 N/A
TB0.CCI2A 0 10 N/A
TB0.2 1
A7#TG425091478, VREF+ X 11 Disabled
JTAG TDO X X TDO
(1) X = don't care
(2) The ADC is not available on the MSP430FR2000 device.