JAJSDR7E February   2016  – December 2019 MSP430FR2310 , MSP430FR2311

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Production Distribution of LPM Supply Currents
    10. 5.10 Typical Characteristics – Current Consumption Per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.12.2  Reset Timing
        1. Table 5-2 Wake-up Times From Low-Power Modes and Reset
      3. 5.12.3  Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 XT1 Crystal Oscillator (High Frequency)
        3. Table 5-5 DCO FLL
        4. Table 5-6 DCO Frequency
        5. Table 5-7 REFO
        6. Table 5-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        7. Table 5-9 Module Oscillator (MODOSC)
      4. 5.12.4  Digital I/Os
        1. Table 5-10 Digital Inputs
        2. Table 5-11 Digital Outputs
        3. 5.12.4.1   Digital I/O Typical Characteristics
      5. 5.12.5  VREF+ Built-in Reference
        1. Table 5-12 VREF+
      6. 5.12.6  Timer_B
        1. Table 5-13 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-14 eUSCI (UART Mode) Clock Frequency
        2. Table 5-15 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-17 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-18 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-19 eUSCI (I2C Mode) Switching Characteristics
      8. 5.12.8  ADC
        1. Table 5-20 ADC, Power Supply and Input Range Conditions
        2. Table 5-21 ADC, 10-Bit Timing Parameters
        3. Table 5-22 ADC, 10-Bit Linearity Parameters
      9. 5.12.9  Enhanced Comparator (eCOMP)
        1. Table 5-23 eCOMP0
      10. 5.12.10 Smart Analog Combo (SAC)
        1. Table 5-24 SAC0 (SAC-L1, OA)
      11. 5.12.11 Transimpedance Amplifier (TIA)
        1. Table 5-25 TIA0
      12. 5.12.12 FRAM
        1. Table 5-26 FRAM
      13. 5.12.13 Emulation and Debug
        1. Table 5-27 JTAG, Spy-Bi-Wire Interface
        2. Table 5-28 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Standard Interface
    8. 6.8  Spy-Bi-Wire Interface (SBW)
    9. 6.9  FRAM
    10. 6.10 Memory Protection
    11. 6.11 Peripherals
      1. 6.11.1  Power-Management Module (PMM) and On-chip Reference Voltages
      2. 6.11.2  Clock System (CS) and Clock Distribution
      3. 6.11.3  General-Purpose Input/Output Port (I/O)
      4. 6.11.4  Watchdog Timer (WDT)
      5. 6.11.5  System Module (SYS)
      6. 6.11.6  Cyclic Redundancy Check (CRC)
      7. 6.11.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.11.8  Timers (Timer0_B3, Timer1_B3)
      9. 6.11.9  Backup Memory (BAKMEM)
      10. 6.11.10 Real-Time Clock (RTC) Counter
      11. 6.11.11 10-Bit Analog-to-Digital Converter (ADC)
      12. 6.11.12 eCOMP0
      13. 6.11.13 SAC0
      14. 6.11.14 TIA0
      15. 6.11.15 eCOMP0, SAC0, TIA0, and ADC in SOC Interconnection
      16. 6.11.16 Embedded Emulation Module (EEM)
      17. 6.11.17 Peripheral File Map
    12. 6.12 Input/Output Diagrams
      1. 6.12.1 Port P1 Input/Output With Schmitt Trigger
      2. 6.12.2 Port P2 Input/Output With Schmitt Trigger
    13. 6.13 Device Descriptors (TLV)
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
    3. 7.3 Typical Applications
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 はじめに
    2. 8.2 デバイスの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Community Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

2 改訂履歴

リビジョン D からリビジョン E への変更点

Changes from August 29, 2018 to December 9, 2019

  • Updated Section 3.1, Related ProductsGo
  • Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in Section 5.3, Recommended Operating ConditionsGo
  • Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in Section 5.3, Recommended Operating ConditionsGo
  • Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3, Recommended Operating ConditionsGo
  • Corrected "SVS Enabled" test condition on Figure 5-2, LPM3.5 Supply Current vs TemperatureGo
  • Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to Table 5-3, XT1 Crystal Oscillator (Low Frequency)Go
  • Changed the note that begins "Requires external capacitors at both terminals..." in Table 5-3, XT1 Crystal Oscillator (Low Frequency)Go
  • Changed the parameter symbol from RI to RI,MUX in Table 5-20, ADC, Power Supply and Input Range ConditionsGo
  • Corrected the test conditions for the RI,MUX parameter in Table 5-20, ADC, Power Supply and Input Range ConditionsGo
  • Added RI,Misc TYP value of 34 kΩ in Table 5-20, ADC, Power Supply and Input Range ConditionsGo
  • Added formula for RI in Table 5-21, ADC, 10-Bit Timing ParametersGo
  • Added the note that begins "tSample = ln(2n+1) × τ ..." in Table 5-21, ADC, 10-Bit Timing ParametersGo
  • Corrected bitfield from RTCCLK to RTCCKSEL in Table 6-8, Clock DistributionGo
  • Corrected bitfield from IRDSEL to IRDSSEL in Section 6.11.8, Timers (Timer0_B3, Timer1_B3) , in the description that starts "The interconnection of Timer0_B3 and ..."Go
  • Added P1SELC information in Table 6-31, Port P1, P2 Registers (Base Address: 0200h)Go
  • Added P2SELC information in Table 6-31, Port P1, P2 Registers (Base Address: 0200h)Go
  • Added note to "ADC calibration" in Table 6-46, Device DescriptorsGo

Changes from September 12, 2017 to August 28, 2018

  • Updated Section 3.1, Related ProductsGo
  • Added note to VSVSH- and VSVSH+ parameters in Table 5-1, PMM, SVS and BORGo
  • Corrected ADCINCHx column heading in Table 6-16, ADC Channel ConnectionsGo
  • Section 8.2「デバイスの項目表記」のテキストおよび図を更新Go

Changes from June 1, 2016 to September 11, 2017

  • 特長の項目「シャットダウン (LPM4.5)」の電流を訂正Go
  • テスト・データに基づき低リーク電流入力を 50pA から 5pA に改善Go
  • Added Section 3.1, Related ProductsGo
  • Removed ADCDIV from the formula for the TYP value in the second row of the tCONVERT parameter in Table 5-21, ADC, 10-Bit Timing Parameters (removed because ADCCLK is after division)Go
  • Changed the entries for eUSCI_A0 and eUSCI_B0 in the LPM3 column from Off to Optional in Table 6-1, Operating ModesGo
  • Added the sentence that begins "This device supports blank device detection..." in Section 6.6, Bootloader (BSL)Go
  • Added the note "Controlled by the RTCCLK bit in the SYSCFG2 register" on Table 6-8, Clock DistributionGo
  • Added Figure 6-1, Clock Distribution Block DiagramGo
  • Added Figure 6-2, Timer_B ConnectionsGo
  • Removed SYSBERRIV register (not supported) in Table 6-26, SYS RegistersGo
  • Changed from "If the RST/NMI pin is unused...with a 2.2-nF pulldown capacitor" to "If the RST/NMI pin is unused...with a 10-nF pulldown capacitor"Go

Changes from March 30, 2016 to May 31, 2016

  • デバイスのステータスを「製品プレビュー」から「量産データ」に変更 Go
  • Changed the value of fXT1 in the table note that starts "Low-power mode 4, VLO,..."Go
  • Added Test Conditions to module Timer_B in Section 5.10, Typical Characteristics – Current Consumption Per ModuleGo
  • Added "16 MHz" to the parameter description of tFLL, lock in Table 5-5, DCO FLLGo
  • Removed ±3℃ from calibration temperatures in the table note that starts "The device descriptor structure contains calibration values..."Go
  • Changed the unit on the ENI parameter in Table 5-24, SAC0 (SAC-L1, OA)Go
  • Changed the unit on the ENI parameter in Table 5-25, TIA0Go

Changes from February 23, 2016 to March 29, 2016

  • ドキュメント全体で、TIAモジュールの名称をTRI0からTIA0に変更Go
  • Changed TYP values for the IAM, FRAM(0%) parameter in Section 5.4, Active Mode Supply Current Into VCC Excluding External CurrentGo
  • Changed MAX values of the tVALID,SO parameter in Table 5-18, eUSCI (SPI Slave Mode) Switching CharacteristicsGo
  • Changed the TYP value of the CMRR parameter with Test Conditions of "TRIPM = 0" from 70 dB to 80 dB in Table 5-25, TIA0Go
  • Changed the TYP value of the PSRR parameter with Test Conditions of "TRIPM = 0" from 70 dB to 80 dB in Table 5-25, TIA0Go
  • 以前の「開発ツールのサポート」セクションを、Section 8.3「ツールとソフトウェア」に置き換えGo