JAJSDR7E February   2016  – December 2019 MSP430FR2310 , MSP430FR2311

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Production Distribution of LPM Supply Currents
    10. 5.10 Typical Characteristics – Current Consumption Per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.12.2  Reset Timing
        1. Table 5-2 Wake-up Times From Low-Power Modes and Reset
      3. 5.12.3  Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 XT1 Crystal Oscillator (High Frequency)
        3. Table 5-5 DCO FLL
        4. Table 5-6 DCO Frequency
        5. Table 5-7 REFO
        6. Table 5-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        7. Table 5-9 Module Oscillator (MODOSC)
      4. 5.12.4  Digital I/Os
        1. Table 5-10 Digital Inputs
        2. Table 5-11 Digital Outputs
        3. 5.12.4.1   Digital I/O Typical Characteristics
      5. 5.12.5  VREF+ Built-in Reference
        1. Table 5-12 VREF+
      6. 5.12.6  Timer_B
        1. Table 5-13 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-14 eUSCI (UART Mode) Clock Frequency
        2. Table 5-15 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-17 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-18 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-19 eUSCI (I2C Mode) Switching Characteristics
      8. 5.12.8  ADC
        1. Table 5-20 ADC, Power Supply and Input Range Conditions
        2. Table 5-21 ADC, 10-Bit Timing Parameters
        3. Table 5-22 ADC, 10-Bit Linearity Parameters
      9. 5.12.9  Enhanced Comparator (eCOMP)
        1. Table 5-23 eCOMP0
      10. 5.12.10 Smart Analog Combo (SAC)
        1. Table 5-24 SAC0 (SAC-L1, OA)
      11. 5.12.11 Transimpedance Amplifier (TIA)
        1. Table 5-25 TIA0
      12. 5.12.12 FRAM
        1. Table 5-26 FRAM
      13. 5.12.13 Emulation and Debug
        1. Table 5-27 JTAG, Spy-Bi-Wire Interface
        2. Table 5-28 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Standard Interface
    8. 6.8  Spy-Bi-Wire Interface (SBW)
    9. 6.9  FRAM
    10. 6.10 Memory Protection
    11. 6.11 Peripherals
      1. 6.11.1  Power-Management Module (PMM) and On-chip Reference Voltages
      2. 6.11.2  Clock System (CS) and Clock Distribution
      3. 6.11.3  General-Purpose Input/Output Port (I/O)
      4. 6.11.4  Watchdog Timer (WDT)
      5. 6.11.5  System Module (SYS)
      6. 6.11.6  Cyclic Redundancy Check (CRC)
      7. 6.11.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.11.8  Timers (Timer0_B3, Timer1_B3)
      9. 6.11.9  Backup Memory (BAKMEM)
      10. 6.11.10 Real-Time Clock (RTC) Counter
      11. 6.11.11 10-Bit Analog-to-Digital Converter (ADC)
      12. 6.11.12 eCOMP0
      13. 6.11.13 SAC0
      14. 6.11.14 TIA0
      15. 6.11.15 eCOMP0, SAC0, TIA0, and ADC in SOC Interconnection
      16. 6.11.16 Embedded Emulation Module (EEM)
      17. 6.11.17 Peripheral File Map
    12. 6.12 Input/Output Diagrams
      1. 6.12.1 Port P1 Input/Output With Schmitt Trigger
      2. 6.12.2 Port P2 Input/Output With Schmitt Trigger
    13. 6.13 Device Descriptors (TLV)
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
    3. 7.3 Typical Applications
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 はじめに
    2. 8.2 デバイスの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Community Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.12.1 Port P1 Input/Output With Schmitt Trigger

Figure 6-5 shows the port diagram. Table 6-43 summarizes the selection of the port functions.

MSP430FR2311 MSP430FR2310 P1.gif

NOTE:

Functional representation only.
Figure 6-5 Port P1 Input/Output With Schmitt Trigger

Table 6-43 Port P1 Pin Functions

PIN NAME (P1.x) x FUNCTION CONTROL BITS AND SIGNALS(1)
P1DIR.x P1SELx JTAG
P1.0/UCB0STE/SMCLK/ C0/A0/Veref+ 0 P1.0 (I/O) I: 0; O: 1 00 N/A
UCB0STE X 01 N/A
SMCLK 1 10 N/A
VSS 0
C0, A0/Veref+ X 11 N/A
P1.1/UCB0CLK/ACLK/ C1A1 1 P1.1 (I/O) I: 0; O: 1 0 N/A
UCB0CLK X 01 N/A
ACLK 1 10 N/A
VSS 0
C1, A1 X 11 N/A
P1.2/UCB0SIMO/ UCB0SDA/TB0TRG/ OA0-/A2/Veref- 2 P1.2 (I/O) I: 0; O: 1 00 N/A
UCB0SIMO/UCB0SDA X 01 N/A
TB0TRG 0 10 N/A
OA0-, A2/Veref- X 11 N/A
P1.3/UCB0SOMI/ UCB0SCL/OA0O/A3 3 P1.3 (I/O) I: 0; O: 1 00 N/A
UCB0SOMI/UCB0SCL X 01 N/A
OA0O, A3 X 11 N/A
P1.4/UCA0STE/TCK/ OA0+/A4 4 P1.4 (I/O) I: 0; O: 1 00 Disabled
UCA0STE X 01 Disabled
OA0+, A4 X 11 Disabled
JTAG TCK X X TCK
P1.5/UCA0CLK/TMS/ TRI0O/A5 5 P1.5 (I/O) I: 0; O: 1 00 Disabled
UCA0CLK X 01 Disabled
TRI0O, A5 X 11 Disabled
JTAG TMS X X TMS
P1.6/UCA0RXD/ UCA0SOMI/TB0.1/TDI/ TCLK/TRI0-/A6 6 P1.6 (I/O) I: 0; O: 1 00 Disabled
UCA0RXD/UCA0SOMI X 01 Disabled
TB0.CCI1A 0 10 Disabled
TB0.1 1
TRI0-, A6 X 11 Disabled
JTAG TDI/TCLK X X TDI/TCLK
P1.7/UCA0TXD/ UCA0SIMO/TB0.2/TDO/ TRI0+/A7/VREF+ 7 P1.7 (I/O) I: 0; O: 1 00 Disabled
UCA0TXD/UCA0SIMO X 01 Disabled
TB0.CCI2A 0 10 Disabled
TB0.2 1
TRI0+, A7, VREF+ X 11 Disabled
JTAG TDO X X TDO
(1) X = don't care