JAJSDR7E February   2016  – December 2019 MSP430FR2310 , MSP430FR2311

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Production Distribution of LPM Supply Currents
    10. 5.10 Typical Characteristics – Current Consumption Per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.12.2  Reset Timing
        1. Table 5-2 Wake-up Times From Low-Power Modes and Reset
      3. 5.12.3  Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 XT1 Crystal Oscillator (High Frequency)
        3. Table 5-5 DCO FLL
        4. Table 5-6 DCO Frequency
        5. Table 5-7 REFO
        6. Table 5-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        7. Table 5-9 Module Oscillator (MODOSC)
      4. 5.12.4  Digital I/Os
        1. Table 5-10 Digital Inputs
        2. Table 5-11 Digital Outputs
        3. 5.12.4.1   Digital I/O Typical Characteristics
      5. 5.12.5  VREF+ Built-in Reference
        1. Table 5-12 VREF+
      6. 5.12.6  Timer_B
        1. Table 5-13 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-14 eUSCI (UART Mode) Clock Frequency
        2. Table 5-15 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-17 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-18 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-19 eUSCI (I2C Mode) Switching Characteristics
      8. 5.12.8  ADC
        1. Table 5-20 ADC, Power Supply and Input Range Conditions
        2. Table 5-21 ADC, 10-Bit Timing Parameters
        3. Table 5-22 ADC, 10-Bit Linearity Parameters
      9. 5.12.9  Enhanced Comparator (eCOMP)
        1. Table 5-23 eCOMP0
      10. 5.12.10 Smart Analog Combo (SAC)
        1. Table 5-24 SAC0 (SAC-L1, OA)
      11. 5.12.11 Transimpedance Amplifier (TIA)
        1. Table 5-25 TIA0
      12. 5.12.12 FRAM
        1. Table 5-26 FRAM
      13. 5.12.13 Emulation and Debug
        1. Table 5-27 JTAG, Spy-Bi-Wire Interface
        2. Table 5-28 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Standard Interface
    8. 6.8  Spy-Bi-Wire Interface (SBW)
    9. 6.9  FRAM
    10. 6.10 Memory Protection
    11. 6.11 Peripherals
      1. 6.11.1  Power-Management Module (PMM) and On-chip Reference Voltages
      2. 6.11.2  Clock System (CS) and Clock Distribution
      3. 6.11.3  General-Purpose Input/Output Port (I/O)
      4. 6.11.4  Watchdog Timer (WDT)
      5. 6.11.5  System Module (SYS)
      6. 6.11.6  Cyclic Redundancy Check (CRC)
      7. 6.11.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.11.8  Timers (Timer0_B3, Timer1_B3)
      9. 6.11.9  Backup Memory (BAKMEM)
      10. 6.11.10 Real-Time Clock (RTC) Counter
      11. 6.11.11 10-Bit Analog-to-Digital Converter (ADC)
      12. 6.11.12 eCOMP0
      13. 6.11.13 SAC0
      14. 6.11.14 TIA0
      15. 6.11.15 eCOMP0, SAC0, TIA0, and ADC in SOC Interconnection
      16. 6.11.16 Embedded Emulation Module (EEM)
      17. 6.11.17 Peripheral File Map
    12. 6.12 Input/Output Diagrams
      1. 6.12.1 Port P1 Input/Output With Schmitt Trigger
      2. 6.12.2 Port P2 Input/Output With Schmitt Trigger
    13. 6.13 Device Descriptors (TLV)
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
    3. 7.3 Typical Applications
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 はじめに
    2. 8.2 デバイスの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Community Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4.3 Signal Descriptions

Table 4-2 describes the signals for all device variants and package options.

Table 4-2 Signal Descriptions

FUNCTION SIGNAL NAME PIN NUMBER PIN TYPE DESCRIPTION
PW20 RGY PW16
ADC A0 2 2 2 I Analog input A0
A1 1 1 1 I Analog input A1
A2 20 16 16 I Analog input A2
A3 19 15 15 I Analog input A3
A4 18 14 14 I Analog input A4
A5 17 13 13 I Analog input A5
A6 16 12 11 I Analog input A6
A7 15 11 10 I Analog input A7
Veref+ 2 2 2 I ADC positive reference
Veref- 20 16 16 I ADC negative reference
eCOMP0 C0 2 2 2 I Comparator input channel C0
C1 1 1 1 I Comparator input channel C1
COUT 14 10 9 O Comparator output channel COUT
TIA0 TRI0+ 15 11 10 I TIA0 positive input
TRI0- 16 12 12 I TIA0 negative input
TRI0O 17 13 13 O TIA0 output
SAC0 OA0+ 18 14 14 I SAC0, OA positive input
OA0- 20 16 16 I SAC0, OA negative input
OA0O 19 15 15 O SAC0, OA output
Clock ACLK 1 1 1 O ACLK output
MCLK 8 8 8 O MCLK output
SMCLK 2 2 2 O SMCLK output
XIN 7 7 7 I Input terminal for crystal oscillator
XOUT 8 8 8 O Output terminal for crystal oscillator
Debug SBWTCK 3 3 3 I Spy-Bi-Wire input clock
SBWTDIO 4 4 4 I/O Spy-Bi-Wire data input/output
TCK 18 14 14 I Test clock
TCLK 16 12 11 I Test clock input
TDI 16 12 11 I Test data input
TDO 15 11 10 O Test data output
TMS 17 13 13 I Test mode select
TEST 3 3 3 I Test Mode pin – selected digital I/O on JTAG pins
System NMI 4 4 4 I Nonmaskable interrupt input
RST 4 4 4 I/O Reset input, active-low
Power DVCC 5 5 5 P Power supply
DVSS 6 6 6 P Power ground
VREF+ 15 11 10 P Output of positive reference voltage with ground as reference
GPIO P1.1 1 1 1 I/O General-purpose I/O
P1.2 20 16 16 I/O General-purpose I/O
P1.3 19 12 15 I/O General-purpose I/O
P1.4 18 14 14 I/O General-purpose I/O (1)
P1.5 17 13 13 I/O General-purpose I/O (1)
P1.6 16 12 11 I/O General-purpose I/O(1)
P1.7 15 11 10 I/O General-purpose I/O(1)
P2.0 14 10 9 I/O General-purpose I/O
P2.1 13 9 – I/O General-purpose I/O
P2.2 12 – – I/O General-purpose I/O
P2.3 11 – – I/O General-purpose I/O
P2.4 10 – – I/O General-purpose I/O
P2.5 9 – – I/O General-purpose I/O
P2.6 8 8 8 I/O General-purpose I/O
P2.7 7 7 7 I/O General-purpose I/O
I2C UCB0SCL 19 15 15 I/O eUSCI_B0 I2C clock
UCB0SDA 20 16 16 I/O eUSCI_B0 I2C data
UCB0SCL(2) 9 – – I/O eUSCI_B0 I2C clock
UCB0SDA(2) 10 – – I/O eUSCI_B0 I2C data
SPI UCA0STE 18 14 14 I/O eUSCI_A0 SPI slave transmit enable
UCA0CLK 17 13 13 I/O eUSCI_A0 SPI clock input/output
UCA0SOMI 16 12 11 I/O eUSCI_A0 SPI slave out/master in
UCA0SIMO 15 11 10 I/O eUSCI_A0 SPI slave in/master out
UCB0STE 2 2 2 I/O eUSCI_B0 slave transmit enable
UCB0CLK 1 1 1 I/O eUSCI_B0 clock input/output
UCB0SIMO 20 16 16 I/O eUSCI_B0 SPI slave in/master out
UCB0SOMI 19 15 15 I/O eUSCI_B0 SPI slave out/master in
UCB0STE(2) 12 – – I/O eUSCI_B0 slave transmit enable
UCB0CLK(2) 11 – – I/O eUSCI_B0 clock input/output
UCB0SIMO(2) 10 – – I/O eUSCI_B0 SPI slave in/master out
UCB0SOMI(2) 9 – – I/O eUSCI_B0 SPI slave out/master in
UART UCA0RXD 16 12 11 I eUSCI_A0 UART receive data
UCA0TXD 15 11 10 O eUSCI_A0 UART transmit data
Timer_B TB0.1 16 12 11 I/O Timer TB0 CCR1 capture: CCI1A input, compare: Out1 outputs
TB0.2 15 11 10 I/O Timer TB0 CCR2 capture: CCI2A input, compare: Out2 outputs
TB0CLK 7 7 7 I Timer clock input TBCLK for TB0
TB0TRG 20 16 16 I TB0 external trigger input for TB0OUTH
TB1.1 14 10 9 I/O Timer TB1 CCR1 capture: CCI1A input, compare: Out1 outputs
TB1.2 13 9 – I/O Timer TB1 CCR2 capture: CCI2A input, compare: Out2 outputs
TB1CLK 12 – – I Timer clock input TBCLK for TB1
TB1TRG 11 – – I TB1 external trigger input for TB1OUTH
VQFN Pad VQFN Thermal pad – Pad – VQFN package exposed thermal pad. TI recommends connection to VSS.
(1) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to prevent collisions.
(2) This is the remapped functionality controlled by the USCIBRMP bit of the SYSCFG2 register. Only one selected port is valid at any time.

NOTE

Functions shared with the four JTAG pins cannot be debugged if 4-wire JTAG is used for debug.