JAJSEE3 データシート

JAJSEE3D January 2018 – January 2021 MSP430FR2422

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

PW|16
RHL|20

サーマルパッド・メカニカル・データ

発注情報

7.3 Signal Descriptions

Table 7-2 describes the signals for all device variants and package options.

Table 7-2 Signal Descriptions

FUNCTION	SIGNAL NAME	PIN NUMBER		PIN TYPE⁽¹⁾	DESCRIPTION
FUNCTION	SIGNAL NAME	RHL	PW	PIN TYPE⁽¹⁾	DESCRIPTION
ADC	A0	2	2	I	Analog input A0
	A1	1	1	I	Analog input A1
	A2	20	16	I	Analog input A2
	A3	19	15	I	Analog input A3
	A4	13	9	I	Analog input A4
	A5	12	–	I	Analog input A5
	A6	11	–	I	Analog input A6
	A7	10	–	I	Analog input A7
	Veref+	2	2	I	ADC positive reference
	Veref-	20	16	I	ADC negative reference
Clock	ACLK	1	1	I/O	ACLK output
	MCLK	19	15	O	MCLK output
	SMCLK	20	16	O	SMCLK output
	XIN	7	7	I	Input terminal for crystal oscillator
	XOUT	8	8	O	Output terminal for crystal oscillator
Debug	SBWTCK	3	3	I	Spy-Bi-Wire input clock
	SBWTDIO	4	4	I/O	Spy-Bi-Wire data input/output
	TCK	17	13	I	Test clock
	TCLK	15	11	I	Test clock input
	TDI	15	11	I	Test data input
	TDO	14	10	O	Test data output
	TEST	3	3	I	Test mode pin – selected digital I/O on JTAG pins
	TMS	16	12	I	Test mode select
GPIO	P1.0	2	2	I/O	General-purpose I/O
	P1.1	1	1	I/O	General-purpose I/O
	P1.2	20	16	I/O	General-purpose I/O
	P1.3	19	15	I/O	General-purpose I/O
	P1.4	17	13	I/O	General-purpose I/O⁽⁴⁾
	P1.5	16	12	I/O	General-purpose I/O⁽⁴⁾
	P1.6	15	11	I/O	General-purpose I/O⁽⁴⁾
	P1.7	14	10	I/O	General-purpose I/O⁽⁴⁾

	P2.0	8	8	I/O	General-purpose I/O
	P2.1	7	7	I/O	General-purpose I/O
	P2.2	13	9	I/O	General-purpose I/O
	P2.3	12	–	I/O	General-purpose I/O
	P2.4	11	–	I/O	General-purpose I/O
	P2.5	10	–	I/O	General-purpose I/O
	P2.6	9	–	I/O	General-purpose I/O
I²C	UCB0SCL⁽²⁾	19	15	I/O	eUSCI_B0 I²C clock
	UCB0SDA⁽²⁾	20	16	I/O	eUSCI_B0 I²C data

	UCB0SCL⁽²⁾	9	–	I/O	eUSCI_B0 I²C clock
	UCB0SDA⁽²⁾	10	–	I/O	eUSCI_B0 I²C data
Power	DVCC	5	5	P	Power supply
	DVSS	6	6	P	Power ground
	VREF+	1	1	P	Output of positive reference voltage with ground as reference
SPI	UCA0STE	14	10	I/O	eUSCI_A0 SPI slave transmit enable
	UCA0CLK	15	11	I/O	eUSCI_A0 SPI clock input/output
	UCA0SOMI⁽²⁾⁽³⁾	16	12	I/O	eUSCI_A0 SPI slave out/master in
	UCA0SIMO⁽²⁾⁽³⁾	17	13	I/O	eUSCI_A0 SPI slave in/master out
	UCA0SOMI⁽²⁾⁽³⁾	7	7	I/O	eUSCI_A0 SPI slave out/master in
	UCA0SIMO⁽²⁾⁽³⁾	8	8	I/O	eUSCI_A0 SPI slave in/master out

	UCB0STE⁽²⁾	2	2	I/O	eUSCI_B0 slave transmit enable
	UCB0CLK⁽²⁾	1	1	I/O	eUSCI_B0 clock input/output
	UCB0SOMI⁽²⁾	19	15	I/O	eUSCI_B0 SPI slave out/master in
	UCB0SIMO⁽²⁾	20	16	I/O	eUSCI_B0 SPI slave in/master out

	UCB0STE⁽²⁾	12	–	I/O	eUSCI_B0 slave transmit enable
	UCB0CLK⁽²⁾	11	–	I/O	eUSCI_B0 clock input/output
	UCB0SOMI⁽²⁾	9	–	I/O	eUSCI_B0 SPI slave out/master in
	UCB0SIMO⁽²⁾	10	–	I/O	eUSCI_B0 SPI slave in/master out
System	NMI	4	4	I	Nonmaskable interrupt input
System	RST	4	4	I	Active-low reset input
Timer_A	TA0.1	17	13	I/O	Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs
	TA0.2	16	12	I/O	Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs
	TA0CLK	15	11	I	Timer clock input TACLK for TA0

	TA1.1	13	9	I/O	Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs
	TA1.2	12	–	I/O	Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs
	TA1CLK	11	–	I	Timer clock input TACLK for TA1
UART	UCA0RXD⁽²⁾	16	12	I	eUSCI_A0 UART receive data
	UCA0TXD⁽²⁾	17	13	O	eUSCI_A0 UART transmit data

	UCA0RXD⁽²⁾	7	7	I	eUSCI_A0 UART receive data
	UCA0TXD⁽²⁾	8	8	O	eUSCI_A0 UART transmit data
DNC	Do not connect	18	14	–	Do not connect
QFN Pad	QFN thermal pad	Pad	–	–	QFN package exposed thermal pad. TI recommends connecting to V_SS.

(1) Pin Types: I = Input, O = Output, I/O = Input or Output, P = Power

(2) These signal assignments are controlled by the USCIARMP bit of the SYSCFG3 register or the USCIBRMP bit of the SYSCFG2 register. Only one group can be selected at one time.

(3) Signal assignments on these pins are controlled by the remap functionality and are selected by the USCIARMP bit in the SYSCFG3 register. Only one group can be selected at one time. The CLK and STE assignments are fixed and shared by both SPI function groups.

(4) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to prevent collisions.